Abstract: A virtual computer system includes multiple timer emulators for emulating multiple virtual timers in a virtual machine (VM). A time coordinator keeps track of an apparent time that is provided to the multiple timer emulators for presentation to the VM through the virtual timers. In particular, the time coordinator ensures that timer events generated by the multiple timer emulators are presented to the VM in an appropriate sequence and with substantially appropriate relative apparent times. Also, when guest software reads a count from a virtual timer, the time coordinator ensures that the apparent time presented to the guest software is substantially consistent with the apparent times represented by preceding and succeeding timer events. When the apparent time falls behind the real time of the physical computer system, the time coordinator speeds up the apparent time until it catches up to the real time.

Abstract: A virtual computer system including multiple virtual machines (VMs) is implemented in a physical computer system that uses address space identifiers (ASIDs). Each VM includes a virtual translation look-aside buffer (TLB), in which guest software, executing on the VM, may insert address translations, with each translation including an ASID. For each ASID used by guest software, a virtual machine monitor (VMM), or other software unit, assigns a unique shadow ASID for use in corresponding address translations in a hardware TLB. If a unique shadow ASID is not available for a newly used guest ASID, the VMM reassigns a shadow ASID from a prior guest ASID to the new guest ASID, purging any entries in the hardware TLB corresponding to the prior guest ASID. Assigning unique shadow ASIDs limits the need for TLB purges upon switching between the multiple VMs, reducing the number of TLB miss faults, and consequently improving overall processing efficiency.

Abstract: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

Abstract: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

Abstract: In a virtual computer system, the invention virtualizes a primary protection mechanism, which restricts memory accesses based on the type of access attempted and a current hardware privilege level, using a secondary protection mechanism, which is independent of the hardware privilege level. The invention may be used to virtualize the protection mechanisms of the Intel IA-64 architecture. In this embodiment, virtual access rights settings in a virtual TLB are translated into shadow access rights settings in a hardware TLB, while virtual protection key settings in a virtual PKR cache are translated into shadow protection key settings in a hardware PKR cache, based in part on the virtual access rights settings. The shadow protection key settings are dependent on the guest privilege level, but the shadow access rights settings are not.

Abstract: A first software entity occupies a portion of a linear address space of a second software entity and prevents the second software entity from accessing the memory of the first software entity. For example, in one embodiment of the invention, the first software entity is a virtual machine monitor (VMM), which supports a virtual machine (VM), the second software entity. The VMM sometimes directly executes guest instructions from the VM and, at other times, the VMM executes binary translated instructions derived from guest instructions. When executing binary translated instructions, the VMM uses memory segmentation to protect its memory. When directly executing guest instructions, the VMM may use either memory segmentation or a memory paging mechanism to protect its memory. When the memory paging mechanism is active during direct execution, the protection from the memory segmentation mechanism may be selectively deactivated to improve the efficiency of the virtual computer system.

Abstract: A computer has access to a system-formatted data storage unit (DSU) containing a file system and to a raw DSU. A file within the file system constitutes a raw DSU mapping that facilitates access to the raw DSU. The raw DSU mapping appears to be an ordinary file to a storage user, but with the size of the raw DSU. An attempted access to the raw DSU mapping is translated into a corresponding access to the raw DSU. Access to the raw DSU by the storage user may be restricted to a specified region of the raw DSU, by defining an extent within the raw DSU mapping. The raw DSU mapping provides access to the raw DSU with many of the advantages of using a file system, including name persistency, permissions, persistent attributes, locking information for a distributed file system and other extended metadata.

Abstract: The invention relates to managing registers during a binary translation mode in a virtual computing system. A set of registers is saved to memory before beginning to execute a series of blocks of translated code, and the contents of the set of registers are restored from memory later. A status register is maintained for tracking the status of each register within the set, the status indicating whether the contents are valid and whether the contents are saved in memory. Before the execution of each block, a determination is made as to whether the actions taken within the block relative to the registers are compatible with the current status of the registers. If the actions are not compatible, additional registers are saved to memory or restored from memory, so that the translation block can be executed.

Abstract: A computer system has secondary data that is derived from primary data, such as entries in a TLB being derived from entries in a page table. When an actor changes the primary data, a producer indicates the change in a set data structure, such as a data array, in memory that is shared by the producer and a consumer. There may be multiple producers and multiple consumers and each producer/consumer pair has a separate channel. At coherency events, at which incoherencies between the primary data and the secondary data should be removed, consumers read the channels to determine the changes, and update the secondary data accordingly. The system may be a multiprocessor virtual computer system, the actor may be a guest operating system, and the producers and consumers may be subsystems within a virtual machine monitor, wherein each subsystem exports a separate virtual central processing unit.

Abstract: A computer has access to a system-formatted data storage unit (DSU) containing a file system and to a raw DSU. A file within the file system constitutes a raw DSU mapping that facilitates access to the raw DSU. The raw DSU mapping appears to be an ordinary file to a storage user, but with the size of the raw DSU. An attempted access to the raw DSU mapping is translated into a corresponding access to the raw DSU. Access to the raw DSU by the storage user may be restricted to a specified region of the raw DSU, by defining an extent within the raw DSU mapping. The raw DSU mapping provides access to the raw DSU with many of the advantages of using a file system, including name persistency, permissions, persistent attributes, locking information for a distributed file system and other extended metadata.

Abstract: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

Abstract: The invention is used in a virtual machine monitor for a multiprocessing system that includes a virtual memory system. During a software-based processing of a guest instruction, including translating or interpreting a guest instruction, mappings between virtual addresses and physical addresses are retained in memory until processing of the guest instruction is completed. The retained mappings may be cleared after each guest instruction has been processed, or after multiple guest instructions have been processed. Information may also be stored to indicate that an attempt to map a virtual address to a physical address was not successful. The invention may be extended beyond virtual machine monitors to other systems involving the software-based processing of instructions, and beyond multiprocessing systems to other systems involving concurrent access to virtual memory management data.

Abstract: An electronic Personal Information Manager (PIM) including a calendar/scheduling system with an EarthTime™ module is described. In operation, the system tracks different types of times: “local” time, “home” time, and “remote” time. Home time is the time zone of where the user typically spends most of his or her time; this is usually the time zone for the user's home office. Local time is the time for the locality where the user is located physically at any particular instance in time. “Remote” time represents the time zones of the other individuals (i.e., other than the user). The system may show events and appointments in the user's own “local” time (or other user-selected type of time), regardless of where the user is presently located. Using these three types of time (i.e.

Abstract: A computer system having a “browse” connected to an on-line service (e.g., Internet) is providing with a “Quick” marks utility, which lets a user easily organize programs, Web sites, and other items in tabs, and start them with a single click. The utility provides an interface having a manageable lists of marks organized by tabs, folders, and visual icons. Buttons on the Quick marks utility let the user start programs or jump to a Web site. When the user clicks an Internet Quick marks button, the system launches the user's Web browser and connects the user to that Web site. After the browser is launched, the user can continue to click different Quick marks buttons to connect quickly to desired sites. The utility includes an abstraction layer which operates in conjunction with various drivers. The abstraction layer provides an interface allowing applications to communicate with the system and request Quick mark services.

Abstract: A system and methods for synchronizing information in datasets via a communication medium are provided that are suitable for synchronizing even across communication mediums that are susceptible to high latency, non-FIFO (non-First-In-First-Out) delivery order, or other adverse characteristics. According to an aspect of the invention, in an information processing system, a method for synchronizing a first dataset with at least a second dataset via a communication medium includes a step of storing information that is indicative of a first version of user data of the first dataset, wherein the first version has been involved in prior use for synchronizing with the second dataset.

Abstract: A “Camel-Back” Digital Organizer (CDO) system is described that is designed to attach to a cellular phone in the same manner as an auxiliary battery, and to interface with the phone through contact points available in the phone's interface port. The CDO system is preferably implemented as an add-on component which can be easily attached and detached from a phone by a user and, once in place, can dramatically enhance the phone's functionality, converting the phone into a “smart” phone. The CDO unit includes a main housing supporting, on its back or upper surface, a set of input/navigation buttons and a display screen. The set of buttons comprise a circular pad or circular configuration of buttons, placed at the bevel end of the unit, which are designed as a directional navigation disc or “NaviDisc.” The NaviDisc provides for LEFT, RIGHT, UP, DOWN, and SELECT buttons (i.e., five buttons total).

Abstract: A rule-based methodology is described which supports automatic mapping of data fields between different data sets in a data processing environment. If a field cannot be mapped or matched based on name alone (e.g., an identical match), the methodology employs rules to determine a type for the field, based on the field's name. The determined type of the field is then used for matching. The methodology can be employed to match fields which appear dissimilar phonetically but are otherwise appropriate for matching. In the currently-preferred embodiment, rules are stated in form of: regular expression=type. Here, the regular expression member lists the text strings or substring(s) for the field. The rules are ordered in descending preference according to the likelihood that a given rule will correctly identify a field. In this mariner, the methodology allows the task of mapping fields from one data set to another to be entirely automated.