Abstract: A timing signal transferring circuit (10) that may be arranged to stably transfer a timing signal (S1) between two video signal processing circuits that may operate at different clock frequencies has been disclosed. A first timing signal (S1) may be received from a pre-stage video processing circuit (13). The first timing signal (S1) may be synchronous with a pre-stage system clock (C1) and may be set to the vicinity of a center of a screen by a video signal. A second timing signal (S2) may be generated on the basis of first timing signal (S1) and transferred to a post-stage video signal processing circuit (14). Second timing signal (S2) may be synchronous with a post-stage system clock (C2). In this way, a disturbance or distortion of a video on a screen due to a difference in system clock frequency affecting a video signal in the post-stage circuit may be reduced or eliminated.