Abstract: A system and method is disclosed herein for providing column address increment pipelining within a single physically contiguous storage array, such as a left or a right unit of a double unit. Thereby, a multiple bank arrangement is provided within a double unit which permits column address increment pipelining to be performed within each bank thereof.

Abstract: A slurry containing abrasive particles and a dual-valent rare earth ion or suspension of its colloidal hydroxide is especially useful for polishing surfaces, including those used in microelectronics. A suspension of a colloidal dual-valent rare earth hydroxide is especially useful for polishing silica.

Abstract: An arrangement of enhanced drivability transistors is disclosed herein which includes a plurality of conductor patterns, wherein the conductor patterns include ring-shaped portions which enclose device diffusion contacts and the ring-shaped portions form the gate conductors of insulated gate field effect transistors (IGFETs).

Abstract: Disclosed is a semiconductor structure which comprises a transistor having a source implantation and a drain implantation formed in a semiconductor substrate. The transistor further comprises a gate electrode, a gate oxide, and an active area. The source implantation and drain implantation are situated on opposite sides of said active area, and said gate oxide and gate electrode are situated on top of said active region. The transistor further comprises two trench isolations adjacent to said active area, wherein said trench isolations are situated on opposite sides of said active area such that a sidewall of each trench serves as interface to said active area, at least one of said sidewalls of said trench isolations which serves as interface to said active area being sloped having a slope between 90° and 150°, said trench isolations and source implantation and drain implantation enclosing said active area on four sides.

Abstract: A method and structure for an integrated circuit chip which includes forming a storage capacitor in a vertical opening in a horizontal substrate, forming a conductive strap laterally extending from the vertical opening and forming a transistor having a channel region extending along a vertical surface, the vertical surface lying outside of and being laterally displaced from the vertical opening, the transistor being electrically connected to the storage capacitor by an outdiffusion of the conductive strap.

Abstract: The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried-strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.

Abstract: A method of forming spatially offset storage nodes for deep trench-based DRAMs on a semiconductor substrate. The method involves etching trenches in the surface of the substrate, masking adjacent trenches with a resist material, etching exposed trenches to a depth of about 1 micron. Removing the masking and etching all the trenches to form bulbulous regions in the sidewall of the trenches. The adjacent trenches having vertically spaced bulbulous regions are filled with dielectric material to form high capacitance storage nodes.

Abstract: A method of enhancing the aluminum interconnect properties in very fine metalization patterns interconnecting integrated circuits that improves the texture and electromigration resistance of aluminum in thin films. Enhanced performance can be obtained by forming a smooth oxide layer in situ, or by surface conditioning a previously formed oxide layer in an appropriate manner to provide the requisite surface smoothness, then by refining the aluminum microstructure by hot deposition or ex-situ heat treatment.

Abstract: A method of forming a semiconductor device, including forming a substrate with a memory array region and a logic device region, growing a thick gate dielectric over the substrate, forming a gate stack, including a first polysilicon layer, over the thick gate dielectric for the memory array region, forming a thin gate dielectric on the substrate over the logic device region, wherein layers of the gate stack in the memory array region protect the thick gate oxide during the forming of the thin gate dielectric, forming a second polysilicon layer for the gate stack in the logic device region, to produce a resulting structure, wherein a thickness of the second polysilicon layer is at least as thick as the gate stack in the memory array region, planarizing the structure using chemical mechanical polishing (CMP), and patterning the gate stacks in said memory array region and the logic device region.

Abstract: An integrated circuit device is presented. The integrated circuit device of the present invention comprises a semiconductor substrate having a combination of transistor gates formed using a conventional dielectric-capped gate stack for self-aligned diffusion contacts (SAC) as well as a transistor gate structure formed by removing the dielectric-cap gate stack from selected regions of the semiconductor substrate and replacing the dielectric-cap gate stack with a second gate conductor which is patterned using a damascene process.

Abstract: A reactor for corona destruction of volatile organic compounds (VOCs), a multi-surface catalyst for the reactor and a method of making the catalyst for the reactor. The reactor has a catalyst of a high dielectric material with an enhanced surface area. A catalyst layer stack is formed by depositing a high dielectric layer on a substrate and, then depositing a conductive layer on the dielectric layer. The catalyst layer stack is bombarded by low RF energy ions to form an enhanced surface area and to form a protective layer over the conductive layer. Catalyst layer stacks may be joined back to form double-sided catalyst layer stacks. The catalyst layer stack may be diced into small pieces that are used in the reactor or the whole catalyst layer stack may be used.

Abstract: A method and structure for a dynamic random access memory chip includes memory element arrays having bitlines, a sense amplifier shared by the arrays. The sense amplifier includes multiplexors connected to the bitlines, an equalizer circuit connected to the multiplexors and a timer circuit connecting first bitlines to the sense amplifier a time period after second bitlines are sensed by the sense amplifier, wherein the time period is less than the active phase of the row cycle.

Abstract: Disclosed herein is an arrangement of memory cells in which the spacing between back-to-back trench capacitors is defined at less than 1 F spacing. A pure phase edge mask is used to define such trench patterns having less than 1 F spacing. The reduction in the trench-to-trench spacing results in increased separation between the trench and the near edge of the gate conductor. This increase in the trench to gate conductor spacing, in turn, permits the channel doping concentration to be decreased, with a corresponding increase in ON current to be realized. In alternative embodiments, a pure phase edge mask or a blocked phase edge mask can be used to define trench patterns in which the width of trenches is increased to form storage capacitors having higher capacitance. In such embodiments, the spacing between back-to-back trenches can be reduced, such that the total separation between the outer edges of adjacent trenches is maintained at about 3 F or less.

Abstract: A method for counter-doping gate stack conductors on a semiconductor substrate, which substrate is provided with narrow space array regions (i.e., memory device regions) having a plurality of capped gate stack conductors spaced a first distance apart, and wide space array regions (i.e., logic device regions) having a plurality of gate stack conductors spaced a second distance apart, wherein the first distance is narrow in relation to the second distance.

Abstract: A wafer polishing tool is disclosed which includes a polishing platen which is rotatable about a central platen axis, and a wafer carrier which supports a wafer for rotational movement to cause a portion of a surface of the wafer to only intermittently contact a polishing surface of the platen while the wafer rotates. The polishing tool may include a plurality of vertically stacked polishing platens which are rotatable about a central platen axis, and a plurality of stacked wafer carriers, wherein each carrier supports a wafer for rotational movement and vertical movement into contact with one of the polishing platens. During polishing, the carrier pack maintains the wafers in uninterrupted contact with the platen over less than entire surfaces of the wafers.

Abstract: A wordline activation delay monitor circuit is disclosed wherein at least one sample wordline and a sample wordline redundancy are located within the same data-storing array region of a memory, and a sample wordline selector is coupled to activate the sample wordline or sample wordline redundancy based on the state of a nonvolatile input. The wordline selector circuit may include one or both of a row decoder circuit or a wordline driver circuit which have substantially the same structure and location as row decoder circuits and wordline driver circuits used to activate wordlines within the data-storing array region.

Abstract: A method for forming a field effect transistor (FET) is disclosed which includes forming an isolation region in a substrate of semiconductor material, anisotropically etching the substrate such that a sidewall spacer region of semiconductor material remains on a sidewall of the isolation region as a device region of the FET. The isolation region may then be recessed such that, after gate conductor deposition, the central channel region of the device region is enclosed by the gate conductor. A dopant concentration in at least one of the central portion of the device region or regions flanking the central portion are then altered to form source-drain regions having a first dopant type and a channel region having a second dopant type opposite the first dopant type.

Abstract: A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.

Abstract: A method is disclosed for calibrating the oscillation frequency versus control voltage characteristic of a voltage controlled oscillator (VCO). The method includes establishing an oscillation frequency of the VCO at a maximum target frequency value ft_H (point Q) when the control voltage Vc equals a predetermined reference voltage Vref which lies within the operating range of the control voltage Vc, and verifying that the oscillation frequency becomes a minimum target frequency value ft_L when the control voltage Vc is changed to a value between the minimum value Vclamp_L and the reference voltage Vref. An automatically calibrated PLL circuit including a VCO is disclosed which performs a calibration to set the oscillation frequency versus control voltage characteristic of the VCO.

Abstract: The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.