Patents Represented by Attorney Dave L. Guglielmi

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  • Wirebond structure and method to connect to a microelectronic die
    Patent number: 7855103
    Abstract: A wirebond structure includes a copper pad formed on or in a surface of a microelectronic die. A conductive layer is included in contact with the copper pad and a bond wire is bonded to the conductive layer. The conductive layer is formed of a material to provide a stable contact between the bond wire and the copper pad in at least one of an oxidizing environment and an environment with temperatures up to at least about 350° C.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: December 21, 2010
    Assignee: Intel Corporation
    Inventors: Robert J. Gleixner, Donald Danielson, Patrick M. Paluda, Rajan Naik
  • Patterned backside stress engineering for transistor performance optimization
    Patent number: 7821073
    Abstract: Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: October 26, 2010
    Assignee: Intel Corporation
    Inventors: Gilroy J. Vandentop, Rajashree Baskaran