Abstract: A wireless alarm system using spread spectrum transmitters, fast frequency shift keying, spread spectrum receivers and computer with a display. The spread spectrum transmitter includes an oscillator coupled to a microprocessor with chip code generation means, preamble register, address register and data register. The spread spectrum receiver acquires synchronization of the spread spectrum signal using a microprocessor coupled to the quieting, signal strength or baseband output of the receiver, with a two step algorithm. The steps comprise achieving a coarse lock and a fine lock to the spread spectrum signal.

Abstract: A integer encryptor and decryptor, with the integer encryptor comprising a pseudorandom source, a discrete-time source, guard-band means, and adding means. The pseudorandom source generates a random-data signal. The random-data signal is an integer that lies within a first-bounded range. The discrete-time source generates the input-data signal. The guard-band means is coupled to the discrete-time source. In response to the input-data signal, the guard-band means generates an output-data signal. For a second-limit number the guard-band means limits the output-data signal to lie within a second-bounded range. The second-limit number is less than the first-limit number. The modulo-adding means is coupled to the pseudorandom source and the guard-band means. The modulo-adding means repetitively adds the output-data signal with the random-data signal and a third-limit number and generates an encrypted-data signal.

Abstract: A bit density controller is capable of transmitting no more than 15 consecutive 0-bits to be sent serially in a data bit sequence, without a 1-bit, for operating on the AT&T T1 network. The bit density controller includes a state machine having a state index and a substitution device coupled to the state machine. The bit density controller additionally can include a buffer for storing at least one frame of the data bit sequence, a memory for storing overhead bits, and an overhead bit inserter for inserting overhead bits into the data bit sequence.

Abstract: A computation for batch processing public key encryption method using a processor. The method batch processes an e1.sup.th root of a first message-data signal, M1, as M1.sup.1/e1, and an e2.sup.th root of a second message-data signal, M2,. where e1 and e2 are relatively prime, using the steps of computing an exponent product, e, by multiplying e1 times e2; computing a message product, M, wherein M=M1 .sup.(e/e1) M2.sup.(e/e2) ; computing a batch root, R, wherein R=M.sup.1/e ; computing the euclidean inverse, t, of e2 modulo e1; and computing R.sup.e2*t /(M1.sup.(e2*t-1)/e1 M2.sup.t), thereby generating M1 .sup.(1/e1). For a plurality of message-data signals, the method batch processes a plurality of message-data-signal roots as the e1, e2, . . ., ek, roots for a plurality of message-data signals, M1, M2, . . . Mk, respectively, where the ei and ej are pairwise relatively prime for i.noteq.j.

Abstract: A paint brush carrier is provided for holding a paint brush, comprising a pocket clip, a flat member pivotally connected to the pocket clip, a handle clip attached to the flat member for clipping the handle of the paint brush, and a paint brush container attached to the flat member for holding the brush end of the paint brush.

Abstract: A Schilling-Manela encoding codec is provided comprising the steps of storing a block of a data-bit sequence in a memory, calculating parity-check symbols from parity-line symbols having p-bits per symbol along parity lines, and setting the parity-check symbols equal to the modulo-2.sup.p sum of the data symbols. The data-bit sequence and parity-check symbols are transformed from Gray symbols, and the Gray symbols are transformed to modulation symbols. A Schilling-Manela decoding method is provided comprising the steps of storing an encoded data-bit sequence in a memory. The encoded-data-bit sequence includes a parity-check-symbol sequence which is stored in parity-memory cells, and a data-bit sequence which is blocked and stored in information-memory cells. The parity-check symbols and the data symbols along the parity lines in the information-memory cells are found.

Abstract: A Schilling-Manela encoding method is provided comprising the steps of storing a block of a data-bit sequence in a memory, calculating parity-check symbols from parity-line symbols having p-bits per symbol along parity lines, and setting the parity-check symbols equal to the modulo-2.sup.p sum of the parity-line symbols. A Schilling-Manela decoding method is provided comprising the steps of storing an encoded data-bit sequence in a memory. The encoded-data-bit sequence includes a parity-check-symbol sequence which is stored in parity-memory cells, and a data-bit sequence which is blocked and stored in information-memory cells. The parity-check symbols and the parity-line symbols along the parity lines in the information-memory cells are found. The count of each composite cell on a composite-error graph traversed by the path of each of the parity lines having an error is incremented and the largest-number cell in the composite-error graph having the largest number is determined.

Abstract: A flat mail collator is provided having a flat base with a rectangular shape and a handle connected to the flat support. A plurality of leaves having a rectangular shape are connected to the flat base for defining spaces between the adjacent ones of the leaves. The plurality of leaves are coded for a plurality of addresses for sorting mail by address by inserting individual pieces of mail between these. Upon completion of the sorting operation, the mail is removed from the leaves by the lifting the flat base by the handles and tilting the flat base and allowing the sorted mail to slip from between the leaves and remain sorted.