Abstract: An integrated circuit oscillator input cell has an oscillator input pad, an oscillator feedback pad, a core terminal, an inverter and an electrostatic discharge protection circuit. The inverter has an inverter input, which is coupled to the oscillator input pad, and an inverter output, which is coupled to the oscillator feedback pad and the core terminal. The electrostatic discharge protection circuit includes a plurality of N-channel protection transistors, which are coupled to the oscillator input pad. The N-channel protection transistors are the only protection transistors that are coupled to the oscillator input pad.

Abstract: A self-timing circuit with bit cell leakage current compensation provides a worst-case delay for a sense application read of a memory core. The self-timing memory circuit includes a worst-case dummy bit cell, a column of leakage current simulating dummy bit cells, and a dummy sense amplifier. The worst-case dummy bit cell is occupied to a dummy word line and a dummy bit line and is configured to drive the dummy bit line or dummy bit line pair to a first differential state when the dummy word line is asserted. The column of leakage current simulating dummy bit cells are coupled to the dummy tit line and are configured to delay the driving of the dummy bit line to the first differential state due to leakage current between the leakage current simulating dummy bit cells and the dummy bit line or bit line pair.