Abstract: An apparatus maps one of a plurality of redundant memory columns, each having a redundant memory cell, to an address of a defective memory column in a memory device that communicates with an external data bus having one or more data-bit lines and an address bus. An address decoder receives an address signal on the address bus and generates an enable signal to enable the redundant cell of the redundant column when the value of the address signal equals the address of the defective memory column. A bit-select bus has one or more bit-select lines each associated with one of the data-bit lines. Each bit-select line can carry a bit-select signal. Each of a plurality of bit-line selectors is associated with one of the redundant columns and communicates with the bit-select bus. In response to an associated enable signal, each bit-line selector can generate the bit-select signal on the bit-select line associated with a desired data-bit line.

Abstract: A power supply isolation and switching circuit formed in a semiconductor structure which eliminates a parasitic diode effect. The switching circuit receives a first power source and a second power source, and selects between the two sources to provide the selected power source to a load device. The switching circuit includes a first transistor, and second and third transistors. The first transistor is connected to the first power source for selecting the first power source as the supply voltage of the load device. The second and third transistors are connected in series to the second power source for selecting the second power source. The second and third transistors are formed in two separate wells of a first conductivity type that are spaced apart and isolated from each other by a semiconductor region of a second conductivity type different from the first conductivity type.