Patents Represented by Attorney, Agent or Law Firm David C. Hsia
  • Patent number: 6833995
    Abstract: An enclosure is disclosed for housing multiple electronic devices. In one embodiment, the enclosure includes a chassis having a floor and opposing sidewalls. Discrete first and second midplanes, each having an opening formed therein, may be disposed in an interior portion of the chassis on opposite sides of a divider wall. The first and second midplanes may be configured to mate to at least one air displacement unit on a back surface of the associated midplane and to mate to at least one device sled on a front surface of the associated midplane. An opening is formed in each midplane adjacent the associated air displacement unit to permit air to pass through the opening.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: December 21, 2004
    Assignee: 3PARdata, Inc.
    Inventors: Eugene Yan Ki Hsue, Bruce T. Arasato
  • Patent number: 6833634
    Abstract: A disk enclosure includes a first group of one or more power sources that powers a first group of elements in a first power domain and a second group of power sources that powers a second group of elements in a second domain. The disk enclosure also includes a first voltage circuit and a second voltage circuit that are each powered by the first group of power sources and the second group of power sources. The first voltage circuit powers a third group of elements while the second voltage circuit powers a fourth group of elements.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: December 21, 2004
    Assignee: 3PARdata, Inc.
    Inventor: William Joshua Price
  • Patent number: 6823442
    Abstract: A method is provided to allow a system administrator of a utility storage server to provision virtual volumes several times larger than the amount of physical storage within the storage server. A virtual volume is a virtual representation of multiple disks as a single large volume to a host or an application. In one embodiment, a virtual volume comprises an exception list containing the set of differences from dummy base volume consisting of all zeros. This exception list can be made up of address tables that map virtual volume pages to logical disk pages. As storage demand grows, additional storage is allocated for the address tables and the data pages from separate pools of storage. If any of the pools runs low, more logical disk regions are allocated to that pool.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: November 23, 2004
    Assignee: 3PARdata, Inc.
    Inventor: Douglas J. Cameron
  • Patent number: 6815128
    Abstract: A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: November 9, 2004
    Assignee: Micrel, Inc.
    Inventors: Robert W. Rumsey, Martin E. Garnett
  • Patent number: 6769616
    Abstract: In one embodiment of the invention, a MEMS structure includes a first electrode, a second electrode, and a mobile element. The first electrode is coupled to a first voltage source. The second electrode is coupled to a second voltage source. The mobile element includes a third electrode coupled to a third voltage source. A steady voltage difference between the first electrode and the third electrode is used to tune the natural frequency of the structure to a scanning frequency of an application. An oscillating voltage difference between the second electrode and the third electrode at the scanning frequency of the application is used to oscillate the mobile element. In one embodiment, the mobile unit is a mirror.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: August 3, 2004
    Assignee: Advanced Nano Systems
    Inventors: Yee-Chung Fu, Ting-Tung Kuo
  • Patent number: 6762432
    Abstract: A test structure pattern includes a first comb having a first set of tines, and a second comb having a second set of tines of the same width and spacing as the first set of tines. When the test structure pattern is stepped between fields on a wafer, the first comb and the second comb at least partially overlap on photoresist over a scribe lane between the fields. When the photoresist is developed, the overlap of the first comb and the second comb generates a metal comb. Electrical continuity is checked for the metal tines of the metal comb to determine the misalignment of the fields.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: July 13, 2004
    Assignee: Micrel, Inc.
    Inventor: Robert W. Rumsey
  • Patent number: 6762434
    Abstract: A test structure pattern includes a first comb, a second comb, and a serpentine line. The first comb includes a first set of tines of the same orientation. The second comb includes a second set of tines of the same orientation that are interdigitated with the first set of tines. The serpentine line runs between the interdigitated tines of the first metal comb and the second metal comb. The test structure pattern forms a first metal comb, a second metal comb, and a serpentine metal line on a die. Print quality and resolution is tested by checking for electrical continuity in the serpentine metal line and bridging between the serpentine metal line and one of the first metal comb and the second metal comb.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: July 13, 2004
    Assignee: Micrel, Inc.
    Inventors: Robert W. Rumsey, Hiu F Ip, Arthur Lam
  • Patent number: 6677831
    Abstract: A new method to control differential signal trace impedance allows flexible use of different signal trace width and spacing while maintaining constant differential impedance in printed circuit boards. Differential impedance of a signal pair is determined by the geometry of individual traces and the spacing between traces. The value of the differential impedance is inversely proportional to signal trace width and directly proportional to signal trace spacing. By decreasing or increasing trace width and spacing simultaneously, a constant differential impedance can be achieved.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: January 13, 2004
    Assignee: 3PARdata, Inc.
    Inventors: Christopher Cheng, Josh Price
  • Patent number: 6658478
    Abstract: A data storage system includes a plurality of nodes for providing access to a data storage facility. Each node has a computer-memory complex to provide general purpose computing for the node, a node controller to control data transfers through the respective node, and a cluster memory to buffer data for the data transfers. A plurality of communication paths interconnect the nodes, with a separate communication path provided for each two nodes of the data storage system.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: December 2, 2003
    Assignee: 3PARdata, Inc.
    Inventors: Ashok Singhal, Jeffrey A. Price, David J. Broniarczyk, George C. Cameron
  • Patent number: 6657868
    Abstract: An electronic device mount assembly is disclosed for permitting an electronic device to be mounted within an enclosure. In one embodiment, the electronic device mount assembly includes a pair of braces operable to be secured to opposing sides of an electronic device mount assembly. Each of the braces having at least one fastener mounted thereon. A base member is also disclosed that includes raised connection assemblies operable to receive the fasteners of the first pair of braces, for securing the electronic device to the base member.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: December 2, 2003
    Assignee: 3PARdata, Inc.
    Inventor: Eugene Yan Ki Hsue
  • Patent number: 6649932
    Abstract: A test structure pattern includes a first comb, a second comb, and a serpentine line. The first comb includes a first set of tines of the same orientation. The second comb includes a second set of tines of the same orientation that are interdigitated with the first set of tines. The serpentine line runs between the interdigitated tines of the first metal comb and the second metal comb. The test structure pattern forms a first metal comb, a second metal comb, and a serpentine metal line on a die. Print quality and resolution is tested by checking for electrical continuity in the serpentine metal line and bridging between the serpentine metal line and one of the first metal comb and the second metal comb.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: November 18, 2003
    Assignee: Micrel, Inc.
    Inventors: Robert W. Rumsey, Hui F Ip, Arthur Lam
  • Patent number: 6609265
    Abstract: A bridge expansion joint assembly includes at least a first expansion module and a second expansion module on opposing bridge structures. The first expansion module includes a first hinge pivotally mounted to a first bridge structure so the first hinge can rotate about a first axis, and a first group of fingers pivotally mounted to the first hinge so the first group of fingers can rotate about a second axis. The second expansion module includes a second hinge pivotally mounted to a second bridge structure so the second hinge can rotate about a third axis, and a second group of fingers mounted, either fixedly or pivotally, to the second hinge. The first group of fingers and the second group of fingers are interdigitated and rest upon a sliding support.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: August 26, 2003
    Inventor: Thomas C. Jee
  • Patent number: 6549679
    Abstract: An automated picture montage method (10) and associated apparatus computer system (12) for accepting an original image (40) and a picture database (28) for creating a montage image (58) from a plurality of pictures (46) to approximate the original image (40). In a pre-index database operation (36), the database (28) is indexed so as to minimize the computational power required. In order to maximize the quality of image, tile regions (42) are analyzed beginning at a center tile region (54) in an outward spiraling order of progression (48). In order to speed the process, analysis is accomplished in a first pass operation (44) and a second pass operation (50). Pictures in the picture database (28) are first selected based on the average color difference of the pictures and the tile region (42). A best match picture is found based on the RGB mean square difference between picture subregions and tile subregions.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: April 15, 2003
    Assignee: ArcSoft, Inc.
    Inventor: Juneng Zheng
  • Patent number: 6427991
    Abstract: A non-contact holder including one or more chucks holds a planar workpiece such as a semiconductor wafer, particularly a thin wafer. Each chuck in the holder includes a cavity that opens to a surface adjacent to the workpiece. A tangential orifice introduces a tangential gas flow into the cavity to create a vortex having a central, low-pressure region. A central orifice directs a gas flow into the low-pressure region of the vortex. The combination of gas flows creates a more uniform vacuum attraction holding a workpiece in close proximity to the chuck. The gas exiting from the chuck provides a cushion that prevents contact between wafer and chuck. Small diameter chucks located close to each other help avoid distortion when processing very thin workpieces. In addition to equalizing pressure, the central gas flow increases the angular spread of gas exiting from each chuck and thus simplifies the design of a holder providing a gas flow that inhibits entry of contaminants between the holder and the workpiece.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: August 6, 2002
    Assignee: Tru-Si Technologies, Inc.
    Inventor: Sam Kao
  • Patent number: 6386631
    Abstract: Provided is a vehicle seat assembly which can prevent a submarine phenomenon in a reliable manner, and which is simple in structure so as to allow a high level of flexibility in layout. A slip preventing member for preventing the vehicle occupant from slipping forward under the seat belt in case of an impact is supported by a fixed part of a seat so as to be pivotable between a retracted position and a raised position, and an actuator is interposed between a fixed part of said seat and a part of said slip preventing member. To retain the slip preventing member at its raised position even after the power of the power unit is all used up, the assembly further includes a lock mechanism for retaining said slip preventing member at said raised position.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: May 14, 2002
    Assignee: NHK Spring Co., Ltd.
    Inventors: Kou Masuda, Hiroyoshi Yamaguchi, Tomoharu Ohi, Minoru Takakura
  • Patent number: 6349546
    Abstract: A heat exchanger is used to transfer heat from water to liquid nitrogen. As heat is transferred from the water to the liquid nitrogen, the temperature of the water becomes lower and the liquid nitrogen converts to gaseous nitrogen. The cooled water and gaseous nitrogen are used by one or more semiconductor fabrication equipment in the semiconductor fabrication process. Thus, overall power consumption of the semiconductor fabrication process is lowered because water is cooled by passing the water by liquid nitrogen to convert the liquid nitrogen to gaseous nitrogen for use in the semiconductor fabrication process.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: February 26, 2002
    Assignee: WaferMasters Incorporated
    Inventor: Woo Sik Yoo
  • Patent number: 6327183
    Abstract: A voltage control circuit that narrows the distribution of threshold voltages of memory cells by using nonlinearly incremented programming voltages. To do so, the voltage control circuit applies to the memory cells a first program pulse of a first voltage, a second program pulse of a second voltage to the memory cell, and a third program pulse of a third voltage, where the difference between the third voltage and the second voltage is less than the difference between the second voltage and the first voltage.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: December 4, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph G. Pawletko, K. Michael Han, Narbeh Derhacobian
  • Patent number: 6304487
    Abstract: A voltage control circuit that programs or erases memory cells comprises an internal voltage value store, a register device selectively coupled to an external voltage value source or the internal voltage value store to receive a voltage value, a voltage output circuit coupled to the register device to receive the voltage value and to output a corresponding voltage to the memory cells, and a verify circuit determining the time to successfully program or erase the memory cells. The register device allows the memory cells to be programmed or erased with voltage values designated by the external voltage value source to determine programming and erasing characteristics of the memory cells. Voltage values producing acceptable programming and erasing characteristics are saved in the internal voltage value store.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: October 16, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph G. Pawletko, Binh Quang Le, Pau-Ling Chen, James M. Hong
  • Patent number: 6295228
    Abstract: A programming control circuit programs a memory cell in accordance to a programming signal value that can be varied by a test equipment. The programming control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the programming signal value. The test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the programming signal value. The signal output circuit converts the programming signal value into a programming signal and outputs the programming signal to the memory cell. The verification circuit determines whether the memory cell is successfully programmed. If the memory cell is not successfully programmed, the programming control circuit increases the programming signal value.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: September 25, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph G. Pawletko, Binh Quang Le, Pau-Ling Chen, James M. Hong
  • Patent number: 6276777
    Abstract: A variable maximum operating temperature for a printhead is defined and utilized within both a system and a method. The variable maximum operating temperature varies according to one or more operating conditions within a printer into which the printhead may be installed. If a detected temperature of the printhead is greater than the variable maximum operating temperature for a detected operating condition, the printer will be shut down to prevent overheating. Accordingly, the system and method extend the useful life of the printhead and reduce paper waste.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: August 21, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Stefano Schiaffino, Sebastia Castelltort, David H. Donovan