Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power source for generating a low power supply voltage on the order of 3 V or less. A wordline driver includes a booster for boosting the supply voltage to produce a wordline read voltage which is higher than the supply voltage, and applying the wordline voltage to a wordline. An upper clamp limits a maximum value of the wordline voltage to prevent read disturb. The upper clamp can be configured to reduce an amount by which the maximum value varies with the supply voltage, or to limit the maximum value to substantially a predetermined value.

Abstract: A Universal Serial Bus (USB) controller includes an allocation unit configured to allocate bandwidths to a plurality of nodes in a polling list, each node being capable of storing at least one descriptor representing a respective polling signal. The nodes are arranged in a binary tree structure having a plurality of leaf nodes, a root node, and at least one level of intermediate nodes which are successor nodes for the leaf nodes and predecessor nodes for the root node. The allocation unit is configured to store variables P and S for each node, where P is a maximum bandwidth of polling signals entering a node from predecessor nodes, and S is a sum of bandwidths of polling signals represented by descriptors stored in the node and all successor nodes thereof. It assigns a new device to a node such that a maximum value of P+S for the nodes at each level is minimized. The allocation unit adds a descriptor representing a new polling signal to a node in a specified level which has a minimum value of P+S.

Abstract: A medical teaching doll is provided with devices for simulating the differences between normal organs, and organs which are physically altered by sickle cell or other disease. The devices simulate the normal and diseased conditions so that the differences can be clearly seen and/or felt. The doll is used to train parents to recognize the signs or symptoms of sickle cell disease so that they may seek medical care for their children before they become more acutely ill. The signs or symptoms which are simulated by the doll include change of color of eye sclera, enlargement of spleen, elevated temperature, labored breathing and/-or coughing, and change of color of skin.

Abstract: A semiconductor structure includes a substrate, a microelectronic device formed on the substrate, and a dielectric layer including silicon dioxide formed over the microelectronic device. The silicon dioxide layer is doped with phosphorous in the form of approximately 96% SiO.sub.2 and 4% phosphorous (PH.sub.3) by weight, and has high etch selectivity, polish rate and gettering capability as well as excellent step coverage. The present process also improves uniformity and process control because phosphine is a gas and does not have to be vaporized prior to deposition.

Abstract: A malfunction in a photolithographic fabrication track is detected by applying photoresist to a semiconductor wafer, and exposing the wafer to substantially identical light images in multiple locations using a stepping printer. The light images are defined by an optical reticle and include a plurality of lines or other features that are spaced from each other at approximately the resolution limit of the printer. Developer is applied to the wafer to produce visible images corresponding to the light images. The visible images function as diffraction gratings which reflect light from the wafer. The visible images are inspected optoelectronically or manually. A malfunction is determined to exist if the visible images are not substantially identical.

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate. The state of erasure of the cells is determined by sensing the source voltage of the cells. An erase pulse is applied to the cells by a power supply which applies a source pull-up voltage to the cells configured in accordance with a predetermined function of the state of erasure. The power supply includes a variable current source and/or a resistor which are continuously adjusted as the erase operation progresses to provide an optimal vertical field across the tunnel oxide layers of the cells. Alternatively, the power supply can include a voltage regulator which is continuously adjusted to directly apply an optimal source voltage to the cells. The state of erasure can also be predetermined as a function of time or applied erase pulses, and the power supply adjusted in an open loop manner.

Abstract: A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.

Abstract: A NAND type flash Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of memory cells which each include a floating gate for storing charge when the cell is programmed. Select lines are used to control programming, reading and erasing of the cells. The floating gates and the select line are integrally formed from a first polysilicon layer (POLY 1). A contact area of the select line which is used to make external connection through a vertical interconnect (via) is made thicker than the floating gates to avoid punchthrough of the contact area during a dry etching step which is used to form the via. The POLY 1 layer is first formed to an initial thickness, and a silicon nitride mask layer is formed over the POLY 1 layer. The portion of the silicon nitride layer over the contact area is protected with photoresist, and the remaining area of the silicon nitride layer is etched away.

Abstract: Electrical parameter testing and performance testing are performed on a plurality of microelectronic devices to obtain parametric values and performance values respectively. The parametric values are applied as inputs to a computer program such as a back propagation neural network engine which generates a performance prediction model by self-learning that implements a function relating the performance values to the parametric values. The model is used to predict the performance of devices being fabricated by performing electrical parameter testing on these devices and applying the resulting parametric values to the model as inputs to produce predicted performance values as outputs. The model can be configured to produce predicted performance values as percentages of devices having speed or other parameters in predetermined respective ranges. The model can be further configured to produce predicted performance values as percentages of devices having different types of defects.

Abstract: A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate. The memory further includes a resistive power supply, a sensor, and a controller which cooperates with the power supply. The power supply applies a source voltage to the sources of the cells that can have a maximum value. An erase pulse is applied to the cells during which the power supply is configured to allow the source voltage to clamp to the maximum value. A monitoring pulse is then applied to the cells during which the power supply is configured to prevent the source voltage from clamping to the maximum value. The sensor senses the source voltage while the monitoring pulse is applied. As the source voltage is not clamped, it is substantially a function of band-to-band tunneling current and accurately indicates the average state of erasure of the cells.

Abstract: An application binary interface includes linkage structures for interfacing a binary application program to a digital computer. A function in a relocatable shared object module obtains the absolute address of a Global Offset Table (GOT) in the module using relative branch and link instructions through the computer's link register. A dynamic linker lazily constructs a Procedure Linkage Table (PLT) and a pointer table for an object module in a process memory image in which space is allocated for the PLT, but the PLT is not initially provided. The pointer table stores absolute addresses of external functions that cannot be reached by relative branching from the module. The PLT receives calls to these functions, gets the absolute addresses from the pointer table and branches to the absolute addresses of the functions. The PLT also receives calls to functions that can be reached by relative branching from the module, and causes relative branching to the functions.