Abstract: An Ft multiplier amplifier employs N similar differential amplifier stages, each including a differential transistor pair. Bases of each pair form stage inputs and collectors of each pair form stage outputs. Inputs of adjacent stages are connected in series by interconnecting the transistor bases of adjacent stages so that each stage receives and amplifies the same input current. Outputs of all stages are connected in parallel so that stage output currents are summed to produce an amplifier output current. Thus the current gain of the amplifier is N times the current gain of each amplifier stage. A set of bias circuits employ voltage dividers across inputs of adjacent stages to provide appropriate bias voltages at the node of connection between the adjacent stages.