Patents Represented by Attorney, Agent or Law Firm David J. Zoetewey
  • Patent number: 6603079
    Abstract: A device used in the formation of interconnected printed circuit boards and the like, the device comprising a rigid dielectric layer; a window in the dielectric layer; and at least two interconnects. Each of the at least two interconnects has a first segment bonded to the dielectric layer on a first side of the window, and a second segment bonded to the dielectric layer on a second side of the window. A portion of the each of the at least two interconnects located between the first and second segments extends across the window between the first and second sides of the window. The interconnects do not cover the entire window.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: August 5, 2003
    Assignee: Mack Technologies Florida, Inc.
    Inventor: Richard M. Biron
  • Patent number: 6600292
    Abstract: A power controller which includes a boost pre-regulator receiving power from a power source providing an input voltage and an input current, and having compensation networks which are dynamically adjusted for power level, the pre-regulator providing power factor correction to maintain a total harmonic distortion of the input current of 2-3% at full power, and less than 5% at all power levels, while the input voltage is anywhere within the range of 95 to 265 VAC; and a forward converter receiving control from a current-mode controller which is in turn under the control of the boost pre-regulator, in order to achieve substantially constant duty cycle of the forward converter over the entire range of power levels.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: July 29, 2003
    Inventor: Ellen James
  • Patent number: 6590398
    Abstract: Methods and devices for testing connectivity between connectors on a circuit board include utilizing a bias board having a photoconductive layer coated with a light-transmissive electrically conductive layer in conjunction with a light source and a voltage source to alternately charge and discharge conductors. A conductor discharged by connecting it to a ground via the bias board is determined to be electrically connected to a previously charged conductor if current flows between the conductor and the ground.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: July 8, 2003
    Assignee: Honeywell Advanced Circuits, Inc.
    Inventor: Yutaka Doi
  • Patent number: 6586687
    Abstract: A printed wiring board (PWB) comprises an inner high density circuit routing component laminated within the wiring board, and plated through holes electrically coupling the inner high density circuit to a conductive pattern located on a surface of the PWB. A preferred method for forming such a PWB comprises: providing a built up high density routing component; providing two wiring boards; laminating the built up routing component between the two wiring boards; and using plated through holes to electrically connect a conductive portion of each of the wiring boards to the built up routing component.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: July 1, 2003
    Assignee: TTM Technologies, Inc.
    Inventors: Bruce W. Lee, David G. Swoboda
  • Patent number: 6576839
    Abstract: A unique bond-ply structure and associated processes for processing of the bond-ply structure and for joining together circuit layer pairs which makes it possible to create a bond-ply having raised structures of conductive material which compensate for shrinkage during sintering thus creating a stress-free and void-free electrically conductive junction between layer-pairs in an interconnect.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: June 10, 2003
    Assignee: Honeywell International Inc.
    Inventors: Richard J. Pommer, Scott Zimmerman, Brad Banister
  • Patent number: 6570374
    Abstract: A vacuum chuck with a conductive circuit embedded.onto it's surface wherein the chuck provides a reliable conductive path for electrical testing as well as reliable and uniform mechanical support over the entire area of a flexible panel to be tested. In one possible form, the chuck comprises an air permeable fine grain porous alumina ceramic module having a surface coated with conductive material wherein the coating is thin enough that it does not prevent air from passing through the conductive material or the ceramic module. The conductive material may also be etched or otherwise formed into a conductive pattern to facilitate testing of a panel.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: May 27, 2003
    Assignee: Honeywell International Inc.
    Inventors: Boris Moldavsky, David Mincemeyer, Jaime Araya
  • Patent number: 6560844
    Abstract: Proper registration between layers of a laminated multi-layer interconnect can be achieved by precisely dimensioning the alignment plate, selecting the materials of which the alignment plate is composed to have the same thermal coefficient of expansion as the layers being laminated, and/or providing the alignment plate with pins sized to be equal to or larger the alignment/registration holes of the layers.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: May 13, 2003
    Assignee: Honeywell International Inc.
    Inventor: Richard J. Pommer
  • Patent number: 6557092
    Abstract: A programmable arithmetic and logic unit (ALU) comprising a plurality of data selectors, the data selectors having corresponding data input lines; a plurality of ALU function input lines wherein the number of ALU function input lines is equal to the number of data input lines on each of the data selectors, and each ALU function input line corresponds to one data input line on each of the data selectors; wherein each of the data input lines of each of the data selectors is connected to the corresponding data input lines of each of the other data selectors and to the corresponding ALU function input line.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: April 29, 2003
    Inventor: Greg S. Callen
  • Patent number: 6539157
    Abstract: Compositions and methods are provided whereby printed wiring boards may be produced that comprise a) a substrate layer, and b) a hollow, mirror-clad optical wave-guide laminated onto the substrate layer. The printed wiring board further comprises a cover material coupled to the wave-guide.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: March 25, 2003
    Assignee: Honeywell Advanced Circuits, Inc.
    Inventor: Yutaka Doi
  • Patent number: 6510392
    Abstract: Methods and apparatus for improved impedance measurements are which allow for shorter delays during recalibration and which eliminate the need to physically disconnect and reconnect test leads after initial calibration has been completed. In particular, an adjustment factor is calculated based on impedances measured during initial calibration and is used to adjust future impedance measurements. Moreover, a plurality of loads having pre-measured impedances are switchably connected to the meter such that re-calibration using said loads may be accomplished without the physical connection or disconnection of test leads. The plurality of loads are preferably incorporated into a test board which also comprises additional test leads and a switching mechanism to alternately connect the various loads and test leads to the meter.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: January 21, 2003
    Assignee: Honeywell Advanced Circuits, Inc.
    Inventors: Yutaka Doi, Stephen L. Tisdale
  • Patent number: 6506332
    Abstract: A method for filling vias in an electronic substrate which includes providing a source of fill material; providing a pressure head coupled to the source of fill material via a fill material inlet, the pressure head further comprising an elongated fill material outlet which is substantially larger than the fill material inlet; placing the pressure head in contact with the electronic substrate; and pressurizing the fill material to inject fill material into the vias of the electronic substrate.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: January 14, 2003
    Assignee: Honeywell International Inc.
    Inventor: Jesse L. Pedigo
  • Patent number: 6500566
    Abstract: A method for making a metal-clad laminate product including: providing a carrier film; depositing directly onto the carrier film a release agent layer, the release agent layer comprising an aqueous soluble polymer; forming a conductive metal layer on the release agent layer, the metal layer having a thickness of less than about 10,000 Angstroms; bonding the metal layer to a circuit board laminate layer; and removing the carrier film from the metal layer by peeling the carrier layer from the release agent layer.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: December 31, 2002
    Assignee: Honeywell International Inc.
    Inventor: Gordon Smith