Abstract: A row decoder that includes circuitry to provide a self-timed bootstrap signal. The self-timed bootstrap signal is generated in response to the selection of the row decoder. At the same time, a capacitive device is charged in order to bootstrap a word line. The self-timed bootstrap signal causes a clock generator circuit to output a clock signal that will be used to bootstrap the word line. The self-timed bootstrap signal may be generated by other row decoders. The generation of the self-timed bootstrap signal by a row decoder is responsive to any variations in that decoder, thus always providing an accurate and precise timing of the clock signal to be used for the bootstrapping.

Abstract: A fast low-to-high voltage translator with immunity to latch-up. The circuit includes a voltage comparator and employs at least one transistor which is used to quickly pull up a node. If further uses another transistor which is capable of limiting the voltage at certain nodes in order to eliminate latch-up if a pumped power supply is provided to the circuit. Latch-up therefore is eliminated during power-up. Other transistors are utilized as voltage drop limiters to limit the voltage drop across other transistors during switching. This provides improved reliability by reducing substrate current and hot carriers.

Abstract: A parallel processing device consists of plural processing pipelines arranged in parallel, decoders which decode processing instructions and outputs them to respective processing pipelines, and a general register in which the processing instruction to be outputted to each of decoders is written in one of its registering sections, or a multiple-port register. The processing instructions are written in the general register or the multiple-port register, wherein the respective registering sections storing the processing instructions are simultaneously specified either by a parallel instruction device, a one-dimensional expanded instruction register, or a two-dimensional expanded instruction register so that their contents are simultaneously outputted to make each of the processing pipelines perform simultaneously. Thus, the simultaneous concentration of a large amount of information can be avoided during the parallel processing operation, eliminating the need for a bus with a large bit number.

Abstract: In a semiconductor memory device comprising a plurality of groups of memory cell blocks, a plurality of groups of predecoder input signal lines respectively connected to predecoders in the memory cell block groups, and a predecoder input signal generator. The predecoder input signal generator sets the predecoder input signal lines of the selected group to either the high level or the low level in accordance with the external address information. A clamping circuit is provided to clamp substantially half the predecoder input signal lines of the unselected group to the high level, and the remaining half to the low level. Because one half of the predecoder input signal lines of the unselected group is clamped to the high level and the remaining half of the unselected group is clamped to the low level, their line loads serve as decoupling capacitors both at the charging and discharging of the predecoder input signal lines of the selected group, so that the power supply noise is reduced in both occasions.

Abstract: A fiber for reinforcing concrete comprises a length of metal wire having a substantially straight central part and offset anchoring parts at its opposite ends, each of which includes an initial straight portion parallel to the central part and offset laterally therefrom, a final straight portion coaxial with the central part, and two opposed oblique portions connecting the initial straight portion to the central part and to the final straight portion, respectively.

Abstract: A method of controlling a stepping motor for supplying a drive current to each of the phase windings thereof in response to control signals. The control signals are formed by combining logically phase exciting signals and overdrive signals in synchronization with a clock pulse signal. Each of the overdrive signals also includes a pulse with a longer width at an earlier stage of a phase exciting duration during which a drive current flows in the stepping motor and a pulse with a shorter width at a later stage of the phase exciting duration. Hence, a small drive current flows in the phase windings after a later stage of the exciting duration, thus reducing power consumption.

Abstract: A differential amplifier compares a potential difference between a first input (A.sub.in) and a second input (V.sub.r) and provides complementary output signals (A, A). The differential amplifier comprises a flip-flop (20) having nodes (N1, N2) and nodes (N3, N4) and a fixing means composed of N-channel FETs (33, 34) having drains connected to the nodes (N3, N4) of the flip-flop circuit (20) and sources connected to a second potential (V.sub.SS) and inverters (31, 32) having inputs to which output signals (A, A) are applied and outputs connected to gates of the N-channel FETs (33, 34). The fixing means detects a potential drop of the output signals (A, A) and fixing the nodes (N3, N4) connected to the nodes (N1, N2) to the second potential (V.sub.SS).

Abstract: A variable frequency dividing circuit according to this invention switches a frequency division ratio immediately after a neew frequency division ratio has been input, and then performs a frequency dividing operation without discarding already counted values. This frequency dividing circuit generates an error signal if a newly input frequency division ratio differs from the previous frequency division ratio and the already counted value is larger than the new frequency division ratio. Furthermore, the frequency dividing circuit performs forcibly a frequency division completion processing according to the consecutively input frequency signal.

Abstract: An apparatus for handling strips of paper removably incorporated in paper strip handling equipment. The apparatus has a box having a window for handling strips of paper, a shutter section for opening and closing the window, a drum section having therein a pooling section for temporarily accommodating strips of paper, and an anti-intrusion portion provided on either one of opposite edges of the shutter section with respect to the opening and closing direction of the shutter for preventing a strip of paper, trash or similar alien substance from being inserted in the apparatus through a clearance formed between the box and the shutter section.