Abstract: A power control latch which is connected to an electronic device having first and second parts which are movable relative to each other between a first position and a second position. The power control latch includes first and second electrically conductive members and a nonconductive member. The first and second electrically conductive members are connected to the first part of the electronic device and the nonconductive member is connected to, and extends outwardly from, the second part. When the first and second parts of the electronic device are in the first position, the first and second electrically conductive members are electrically connected to conduct power. When the first and second parts of the electronic device are in the second position, the nonconductive member extends between the first and second conductive members and prevents electrical connection therebetween.

Abstract: A process and apparatus are disclosed for encoding input signals for transmission by a transmitter. A pattern of binary values is generated which has a predetermined average binary weight. The input signals are modulated with the predetermined pattern of binary values. The modulated signals are encoded with a forward error correction code which provides a predetermined level of coding protection. The average binary weight of the predetermined pattern of binary values is selected to be at least as great as the level of coding protection provided by the forward error correction code.

Abstract: An apparatus and method for storing a momentarily applied binary signal in a non-volatile memory cell and for automatically returning to a state which is indicative of the applied binary signal upon power-up of the non-volatile memory. In one aspect, the non-volatile memory is connected to first and second power busses between which a power source supplies an operating voltage and a programming voltage of a substantially greater magnitude than the operating voltage. The non-volatile memory comprises a memory circuit which is connected between the first and second power busses. The memory circuit includes an input node, an output node, and a non-volatile element which is connected to the input and output nodes. The memory circuit responds to an input binary signal from the input node by latching in a first binary state which is indicative of the input binary signal.