Abstract: A slave controller with block transfer capability for transferring data blocks of between one and two hundred fifty six sixteen bit words between a memory and the VERSA MODULE EUROPE bus (VMEbus). The slave controller comprises a programmable array logic device which receives control and address modifier signals from the VMEbus and an address enable signal from a decoding circuit which provides the address enable signal to the programmable array logic device in response to an address strobe signal provided by the VMEbus. The programmable array logic device being responsive to these signals enables the memory for a read or write operation. The programmable array logic device next provides a write pulse to the memory when data is to be written into the memory at addresses provided by a binary counter.