Patents Represented by Attorney David L. Guglielmi
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Patent number: 8344352Abstract: Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place.Type: GrantFiled: July 18, 2011Date of Patent: January 1, 2013Assignee: Intel CorporationInventors: Juan E. Dominguez, Adrien R. Lavoie, John J. Plombon, Joseph H. Han, Harsono S. Simka
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Patent number: 8268724Abstract: In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed.Type: GrantFiled: November 16, 2009Date of Patent: September 18, 2012Assignee: Intel CorporationInventors: Houssam Jomaa, Christine Tsau
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Patent number: 8242831Abstract: A tamper resistant fuse design is generally presented. In this regard, an apparatus is introduced comprising a plurality of fuses in an integrated circuit device to store values and a plurality of resistors in parallel to the fuses, wherein each fuse includes a parallel resistor to provide a potential dissipation path around the fuse. Other embodiments are also described and claimed.Type: GrantFiled: December 31, 2009Date of Patent: August 14, 2012Assignee: Intel CorporationInventors: Xianghong Tong, Zhanping Chen, Kevin X. Zhang, Zhiyong Ma, Kevin D. Johnson, Jun He
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Patent number: 8199759Abstract: A method and apparatus for enabling ID based streams over Peripheral Component Interconnect Express (PCIe) is herein described. In this regard an apparatus is introduced including a memory ordering logic to order packets to be transmitted over a serial point-to-point interconnect, the memory ordering logic to bypass a stalled first packet with a second packet that arrived after the first packet if the second packet includes an attribute flag set to indicate that the second packet is order independent and if the second packet includes an ID that is different from an ID associated with the first packet. Other embodiments are also described and claimed.Type: GrantFiled: May 29, 2009Date of Patent: June 12, 2012Assignee: Intel CorporationInventors: Abhishek Singhal, David Harriman
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Patent number: 8138239Abstract: In some embodiments, polymer thermal interface materials are presented. In this regard, a thermal interface material is introduced comprising a polymer matrix, a matrix additive, wherein the matrix additive comprises a fluxing agent, and a spherical filler material, wherein the spherical filler material comprises a metallic core with an organic solderability preservative coating. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 23, 2008Date of Patent: March 20, 2012Assignee: Intel CorporationInventors: Ed Prack, Yi Li, Wei Wu
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Patent number: 8119508Abstract: In a metal gate replacement process, a stack of at least two polysilicon layers or other materials may be formed. Sidewall spacers may be formed on the stack. The stack may then be planarized. Next, the upper layer of the stack may be selectively removed. Then, the exposed portions of the sidewall spacers may be selectively removed. Finally, the lower portion of the stack may be removed to form a T-shaped trench which may be filled with the metal replacement.Type: GrantFiled: May 17, 2010Date of Patent: February 21, 2012Assignee: Intel CorporationInventors: Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Robert S. Chau
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Patent number: 8093704Abstract: In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented.Type: GrantFiled: June 3, 2008Date of Patent: January 10, 2012Assignee: Intel CorporationInventors: Eric C. Palmer, John S. Guzek
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Patent number: 8084856Abstract: In some embodiments, a thermal spacer for stacked die package thermal management is presented. In this regard, an apparatus is introduced having a top integrated circuit die, a bottom integrated circuit die, and a thermal spacer between the top and bottom integrated circuit dice, the thermal spacer comprising a heat conducting material and the thermal spacer overhanging and extending parallel with one outside edge of the bottom integrated circuit die. Other embodiments are also disclosed and claimed.Type: GrantFiled: March 26, 2010Date of Patent: December 27, 2011Assignee: Intel CorporationInventor: Xuejiao Hu
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Patent number: 8017022Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including forming a film on a surface of a substrate, the film designed to prevent the seeding of an electroless plating catalyst, laser ablating the surface of the substrate through the film to form trenches, and seeding the surface of the substrate with an electroless plating catalyst. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 28, 2007Date of Patent: September 13, 2011Assignee: Intel CorporationInventors: Houssam Jomaa, Omar J. Bchir, Islam Salama
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Patent number: 8018288Abstract: Embodiments of a high-linearity low-noise amplifier (LNA) are generally described herein. Other embodiments may be described and claimed. In some embodiments, an RF input signal may be amplified with a cascode amplifier. The cascode amplifier may include integrated notch filters to attenuate undesired signals. The cascode amplifier may operate from a large power supply when blockers are present to avoid voltage swing compression at its output. The cascode amplifier may be biased and designed to operate in a class AB mode to produce linear output current to avoid current compression or excessive current expansion.Type: GrantFiled: April 13, 2009Date of Patent: September 13, 2011Assignee: Intel CorporationInventors: Jon S. Duster, Stewart S. Taylor
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Patent number: 8013439Abstract: In some embodiments, an injection molded metal stiffener for packaging applications is presented. In this regard, an apparatus is introduced comprising a microelectronic device package substrate, a microelectronic device coupled with a top surface of the package substrate, and an injection-molded, metal stiffener coupled with the package substrate, wherein the stiffener includes a central opening and at least partially surrounds the microelectronic device. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 30, 2008Date of Patent: September 6, 2011Assignee: Intel CorporationInventor: Sabina J. Houle
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Patent number: 8012808Abstract: Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures.Type: GrantFiled: February 8, 2008Date of Patent: September 6, 2011Assignee: Intel CorporationInventors: Wei Shi, Daoqiang Lu, Yiqun Bai, Qing A. Zhou, Jianqqi He
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Patent number: 7982478Abstract: In some embodiments, a liquid TIM dispense and removal method and assembly is presented. In this regard, a method is introduced including loading an absorbent material of a thermal control unit with a liquid thermal interface material (TIM), pressing the absorbent material against an integrated circuit device causing the liquid TIM to be released, testing the integrated circuit device, and removing the absorbent material from against the integrated circuit device causing the liquid TIM to be reabsorbed. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 29, 2008Date of Patent: July 19, 2011Assignee: Intel CorporationInventors: Nader Abazarnia, Ashish X Gupta, Suzana Prstic
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Patent number: 7975158Abstract: A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 31, 2007Date of Patent: July 5, 2011Assignee: Intel CorporationInventors: Muhammed Elgousi, Jayashree Kar, David G. Figueroa, Srikrishnan Venkataraman
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Patent number: 7960190Abstract: In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 12, 2008Date of Patent: June 14, 2011Assignee: Intel CorporationInventors: Eric J. M. Moret, Pooya Tadayon
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Patent number: 7919859Abstract: Embodiments of the invention include apparatuses and methods relating to copper die bumps with electtomigration cap and plated solder. In one embodiment, an apparatus comprises an integrated circuit die, a plurality of copper bumps on a surface of the die, electromigration(EM) caps substantially covering a mating surface of the copper bumps capable of controlling intermetallic formation between the cooper bumps and solder, and solder plating on the EM caps capable of protecting the EM caps from oxidation prior to packaging.Type: GrantFiled: March 23, 2007Date of Patent: April 5, 2011Assignee: Intel CorporationInventors: Ting Zhong, Val Dubin, Mark Bohr
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Patent number: 7900029Abstract: Methods and apparatus to simplify configuration calculation and management of a processor system are disclosed. An example disclosed method reads system configuration data from registers of a processing system, caches the system configuration data in an allocated memory, and calculates new system configuration data for the processing system by operating on cached data. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 26, 2007Date of Patent: March 1, 2011Inventors: Jason Liu, Kevin Y Li, James Tang, Rahul Khanna
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Patent number: 7791585Abstract: A method of fabricating a flexible display, the method comprising selecting a first flexible sheet and a second flexible sheet; and forming a number of magnetic display elements having magnetically controllable reflectivity between the first flexible sheet and the second flexible sheet. In some embodiments, a display includes pixels having a magnetically controllable reflectivity. The pixels are formed between a pair of flexible non-conductive sheets. Each of the magnetically controllable pixels includes a flexible ring located between the flexible non-conductive sheets. Each of the magnetically controllable pixels also includes magnetic particles located within the flexible ring. The location of the magnetic particles with respect to the flexible non-conductive sheets determines the reflectivity of the pixel. The display is especially suitable for use in connection with portable electronic devices.Type: GrantFiled: November 17, 2006Date of Patent: September 7, 2010Assignee: Intel CorporationInventors: James D. Jackson, Terrance J. Dishongh, Damion T. Searls
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Patent number: 7768079Abstract: Embodiments of the invention generally relate to transistors with high-k dielectric spacer liner to mitigate lateral oxide encroachment. In this regard a semiconductor device is introduced having a substrate, a high-k gate dielectric layer on the substrate, a metal gate electrode on the high-k gate dielectric layer, and a high-k dielectric layer on either side of and adjacent to the metal gate electrode and high-k gate dielectric layer, extending a distance away from the metal gate electrode and high-k gate dielectric layer on the substrate. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 26, 2007Date of Patent: August 3, 2010Assignee: Intel CorporationInventors: Justin S. Sandford, Willy Rachmady
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Patent number: 7760140Abstract: In some embodiments, a multiband antenna array using electromagnetic bandgap structures is presented. In this regard, an antenna array is introduced having two or more planar antennas situated substantially on a surface of a substrate, a first set of electromagnetic bandgap (EBG) cells situated substantially between and on plane with the antennas, and a second set of EBG cells situated within the substrate below the antennas. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 9, 2006Date of Patent: July 20, 2010Assignee: Intel CorporationInventor: Telesphor Kamgaing