Abstract: Burst refresh mode circuitry is provided for a memory having cells in rows and columns, sense amplifiers and Latch N/Latch P driver circuitry, a RAS buffer, refresh counters, address buffers, row decoders, precharge circuitry producing shorting clocks, and a refresh detector circuit coupled to the Latch P circuitry to provide a restore finished (RF) signal indicative that a refresh cycle is substantially completed. Burst refresh mode entry circuitry detects proper conditions for entering burst refresh mode. An auto-refresh burst refresh mode circuit causes the RAS buffer to generate a new internal RAS signal. Burst refresh mode logic has counters to count the number of rows that have been refreshed. The system self-times the refreshing by responding to the restore finished signal. A delay circuit interposes a short delay for the precharge before another row is automatically refreshed in the burst refresh mode. Battery back-up mode circuitry is partially disabled.

Abstract: Equipment for deoiling swarf resulting from machining operations including a deoiling centrifuge and an endless conveyor for supplying the swarf to the centrifuge. The conveyor has a support and sliding surface for the swarf with a grating through which the swarf falls for transfer to the deoiling centrifuge but through which foreign bodies are prevented from passing.

Abstract: A method and system for recycling waste materials enables the treatment of masses of waste including thermosetting plastics materials, high-melting thermoplastics materials, aluminum, wood, paper, fabrics, etc. The mass of waste is first subjected to a grinding process, preferably in two stages, to reduce it to a maximum particle size of the order of 10 mm. The granular material thus produced undergoes a heating and mixing process and is then reduced to sheet or strip form and simultaneously cooled in order to undergo a scraping or shaving process which leads to the formation of a mass substantially comparable to a powder with a particle size of between 50 and 1000 microns, including a certain quantity of fibres.

Abstract: A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common wordline (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell.