Abstract: A combined removable hard disk drive and removable memory card mechanical lock which provides a portable computer user with an easy and cost effective arrangement to lock inside the computer expensive modular components such as a hard disk drive and memory cards. When installed on a portable computer, the combined lock will prevent the removable hard disk drive and removable memory cards from being removed from the portable computer.

Abstract: Method and apparatus for power management of a RAM subsystem of a computer. Blocks of data stored at various addresses throughout the RAM subsystem are packed into unallocated memory space at the lowest possible physical location within the RAM subsystem and then are compressed. The packed and compressed data is then copied into the minimum number of RAM devices comprising the subsystem needed to store such data. The remaining RAM devices are either deenergized, if they comprise static RAM, or not refreshed, if they comprise dynamic RAM, thereby reducing the power consumption of the subsystem. Upon a command to return from the reduced power consumption mode, the above steps are executed in the reverse order and the blocks of data are copied to their original memory address locations in said RAM subsystem, using a table that is compiled during the packing step.

Abstract: A memory write disable circuit which disables write operations to main memory during cache diagnostics and thus provides a generic means for testing cache memory systems. Disabling write operations to main memory allows the diagnostics to easily distinguish between cache hits and cache misses during diagnostics. The disable circuit operates by disabling the output enable for the main memory write signal. This disables writes to main memory in a manner external to the memory controller and thus allows tags to be loaded from a cacheable space in main memory. This enables the testing of cache memory systems in computer systems using integrated cache and memory controllers which prevent read hits to memory addresses whose cacheability has been disabled. This also provides a testability function that is hardware independent and thus can be used regardless of the configuration or processor used in the computer system.

Abstract: A system is disclosed for providing a supplemental front lighting system for a liquid crystal display. Retractable light sources are provided adjacent to the LCD. The light sources may be placed in a closed position for compactness when storing the system or when ambient lighting is adequate. The light sources may be placed in an open position when supplemental lighting of the LCD is desired. A grazing incidence reflecting film having a micro replicated surface is applied to the front surface of the LCD to increase light transmission and to collimate and direct light toward the LCD. Multifaceted microstructures arranged in longitudinal columns on the front surface of the film reduce reflection of light at glancing angles, thereby providing for improved and even lighting across the entire LCD.

Abstract: An improved liquid crystal display (LCD) is provided having a static random access memory located within each liquid crystal control cell and between each display electrode and corresponding bit and word lines. The memory cell, or storage cell, includes a pass-gate transistor which, upon activation via word line, forwards bit line video data to a memory circuit, such as a latching circuit, placed between the pass-gate transistor and the display electrode. The latching circuit may consist of two thin-film transistors connected as cross-coupled inverters for latching video data upon the display electrode for virtually an indefinite period of time or until the pass-gate transistor is again activated. By utilizing a storage cell with buffer capability adjacent each display electrode, problems associated with large data line current can be minimized. Moreover, the static memory can rid the host processor of having to continuously refresh the LCD active matrix.

Abstract: A system for refreshing selected portions of a dynamic access memory (DRAM) subsystem of a computer. A memory controller of the present invention includes a RAM device for storing a plurality of region descriptors used to inhibit the refresh of address ranges of the DRAM that do not contain valid data, thereby conserving energy required to refresh the entire DRAM. The controller includes logic circuitry connected between a refresh period timer and the RAM device for inhibiting receipt by a RAS generator of a refresh pulse when a generated refresh address falls within the refresh address range defined by the region descriptor. A refresh address output by a refresh address counter compared to the region descriptors in the RAM device, and if the region descriptors indicate that the row addressed by the refresh address does not contain valid data, the RAS generator is inhibited from producing a RAS pulse.

Abstract: A memory channel array configuration wherein two or more memory channels are used for data transfer and data is striped across each of the memory channels. In addition, one or more redundant memory channels, preferably a single dedicated parity channel, are used for error correction. In the preferred embodiment the memory channel configuration utilizes RAMBUS based memory channels, and thus the present invention provides error correction for a RAMBUS based memory system. Also, the use of multiple memory channels in conjunction with data striping across each of the channels allows for much higher data transfer bandwidths than is available using prior art implementations of RAMBUS technology.

Abstract: A device in which functions of both a conventional mouse and a numerical data entry keypad are integrated into a single unit is disclosed. A conventional mouse ball is disposed on the bottom of the device. Pointer select buttons are disposed on a forward portion of the top of the device and numerical entry keys are disposed on a rearward portion of the top of the device. A microprocessor responsive to the ball, buttons, and keys, generates appropriate signals for input to a single I/O port in a computer. A hood is also provided which is hingedly attached to the device between the forward and rearward portions thereof such that it is rotatable between a first position in which the numerical data entry keys are rendered accessible, thereby enabling the device to function as a numerical keypad, and a second position, in which the numerical data entry keys are rendered inaccessible, thereby enabling the device to function as a conventional mouse.

Abstract: A system for inductively coupling power and data to a portable electronic device. A portable device, such as a personal digital assistant, is powered or recharged via an inductive link between the device and a support unit, thereby eliminating the need for cabling or other connections therebetween. The same inductive link is also used to transfer data signals between the device and a second electronic device, for example, a conventional desktop computer. The support unit includes a primary winding of a transformer, a power amplifier and a modulator. The portable device includes a secondary winding connected in parallel with the input of a rectifier, the output of which is connected to a battery charging circuit, and to a modem, which is further connected to the device microprocessor. Placement of the device on the support unit effects the inductive coupling when the primary and secondary windings are in proximity to one another.

Abstract: A sensor circuit for monitoring the operation of a fan in an electronic device includes a current sensor that produces a voltage signal proportional to the magnitude of the current flowing through the fan. The proportional voltage signal is filtered to extract an rms dc signal that then is compared with a minimum and maximum voltage threshold in two voltage comparators. If the voltage of the filtered signal exceeds the maximum threshold value, or is less than the minimum threshold value, a fan failure signal is generated and transmitted to an external monitoring unit. The sensor circuit can be implemented with a standard two-wire fan and interface connector.

Abstract: Disclosed are an apparatus and method for testing a direct memory access ("DMA") controller. The apparatus comprises (1) a virtual control device including a virtual control latch, the virtual control device coupled to a request input of the DMA controller and capable of transmitting a signal to the DMA controller representing a request to transfer data and (2) a virtual input/output ("I/O") device including a virtual I/O latch, an acknowledgement output of the DMA controller coupled to the virtual I/O device, the virtual I/O latch capable of storing the data for use by the DMA controller. In its preferred embodiment, the present invention operates within the confines of IBM-compatible personal computer architecture, allowing DMA controller functionality to be tested directly.

Abstract: Method and apparatus for effecting BIOS independent power management of a personal computer system having a processor complex connected via a system bus to at least one I/O device capable of operating in a reduced power consumption state. A power control system comprising a dedicated power management microcontroller monitors the activity of various I/O devices. When a particular device or combination of devices has remained inactive for the preselected time interval, the power control system issues a bus request to a processor complex. When the processor complex acknowledges the bus request, the power control system asserts control as master of the system bus and performs the operations necessary to cause at least one device to enter a reduced power consumption state. The power control system then surrenders control of the bus to the processor complex. In one aspect, a CPU clock controller is utilized to reduce the processing speed of the processor complex CPU.

Abstract: A system for processing merchandise sale transactions for customers in a point of sale and warehouse facility. A main processor has a database for storing customer identification information and merchandise information and processes sale transaction records for customers. A point of sale system coupled to the processor has a controller and at least one pen-based computer in communication with the controller via RF transmissions. Program instructions respond to entry on the computer of a customer number and to entry of merchandise identification numbers to build a sale transaction record of selected items for purchase. The program instructions display item information and enable selection of items for addition to the sale transaction record, display delivery method instructions and enable their selection for addition to the sale transaction record, and transmit the transaction record to the processor to effectuate warehouse delivery of the selected items according to the selected delivery instructions.