Abstract: Systems and methods use cyclical propellers with dynamic blade angle control to extract power from waves. A control system for such implementations can adapt pitching schedules for the blades of the cyclical propellers for efficient energy extraction and/or to control reactive forces. The cyclical propellers may be installed on the floor of a body of water or other liquid, on a submarine, or on a surface float, and blades may extend vertically or horizontally depending on the character of the waves. Several cyclical propellers can be combined into a single unit operated to minimize reactive forces and torques, to propel the unit horizontally or vertically, and/or to stabilize the unit. Such units can be installed with minimal or no moorings.

Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.

Abstract: A channel estimation section 112 estimates the states of channels used for pieces of mobile station apparatus (A) and (B), using signals demodulated by radio processing sections 110, 111. A best SIR calculation section 118 calculates coefficients to be used for signal transformation by inverse matrix calculation, using the above channel estimation values by the above channel estimation section 112. A signal transformation section 119 performs linear transformation of transmission signals to the above pieces of mobile station apparatus, using the above coefficients from the above best SIR calculation section 118. Radio processing sections 120, 121 modulates each transmission signal after the above linear transformation for transmission through antennas 108, 109, respectively.

Abstract: A manipulator for a fiber optic cable assembly (FOCA) provides microradian accuracy in control of the direction of a beam emanating from the FOCA. Such manipulators can control FOCAs to control the incidence angles of beams at a beam combiner in a beam-combining unit. Accordingly, fewer additional optical elements are required for control of input paths in the beam-combining unit. The manipulator and the beam-combining unit are accurate enough for use in an interferometer that combines beams with different frequencies and polarizations. One such interferometer includes a Zeeman split laser providing a heterodyne beam. A beam splitter separates frequency components of the beams, and AOMs increase the frequency separation between the separated beams. The separated beams can be sent via optical fibers to the beam-combining unit, which combines the beams for use in interferometer optics.

Abstract: A novel super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid-process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

Abstract: An integrated circuit includes a monitor port, several circuit modules, and a selection circuit that selects which of the circuit modules drives internal signal through the monitor port. A debugging process can observe the internal signals at the monitor port to identify problems in the integrated circuit. In one embodiment, the selection circuit includes a trace bus that runs serially from the monitor port to each circuit module. Each module has tri-state buffers that connect the module to the trace bus. Alternatively, the selection circuit includes a multiplexer with input ports coupled to the modules. A trace select register controls which module drives the monitor port, and control registers or the current operation of each module select which set of internal signals the module applies to the tri-state buffers. Any of large number of internal signals can be selected and observed by programming the trace select register and the configuration registers for the modules.

Abstract: A host signal processor (HSP) modem has a software interface between HSP modem hardware and native audio hardware in a host computer. No hard wire connections between modem hardware and audio hardware are required for synchronization. Instead, a software clock recovery system matches a transfer rate of the HSP modem hardware and a transfer rate of the audio hardware by duplicating or deleting samples. The software interface allows the native audio hardware to make audible the handshaking sequence during modem connections which eliminates the need for a speaker and speaker drivers in the modem hardware. The combination of HSP modem hardware, audio hardware, and software executed by the host computer also allows the HSP modem to perform voice communication such as telephone or speakerphone functions.

Abstract: A memory architecture for a circuit such as a host adapter provides sections of memory used for different types of information and programmable sizes for the sections. Thus, the circuit can adapt memory configurations for different applications. Each section is divided into pages, and for each section, the circuit has a range of internal addresses that map to a current page in the section. Additionally, the circuit has several operating modes and several register sets. Each mode has a set of functions that the circuit performs and a register set that the circuit can access while operating in the mode. Currently accessible pages in the memory are selected according to the operating mode. In particular, the register sets include registers for pointers that identify pages currently accessible. When the circuit switches modes, the accessible register set changes, and changing the register set changes the pointers and which pages are accessible.

Abstract: A photo-ionization detector (PID) includes an ultraviolet (UV) lamp that transmits UV light into an ionization chamber to ionize volatile gases. An ion detector in the ionization chamber includes interdigital electrodes that collect resulting ions using an electrical field perpendicular to the UV light propagation. A pump in the PID circulates gases through the ionization chamber in a direction perpendicular to the electrical field and to the UV light propagation. The PID additionally provides a UV monitor having interdigital electrodes that release electrons when struck by the UV light. The size of a monitor current in the UV monitor indicates the intensity of the UV light. The UV monitor is in a UV monitor chamber that protects the UV monitor from exposure to the ionized gases and improves the accuracy of UV intensity measurements.

Abstract: A semiconductor memory device is disclosed. The device can be controlled by a controller for another less integrated memory device. The device includes a set of a first memory cell array and a second memory cell array having word lines, a row decoding unit which simultaneously activates the first memory cell array and the second memory cell array, and pairs of input and output lines through which data transfer from and to the first memory cell array and the second memory cell array. The row decoding unit includes a decoder which decodes the row address, a first word line driver, and a second word line driver. The first word line driver, which connects to the power supply voltage, transmits the decoded row address to the first memory cell array so as to select the word lines corresponding to the row address among the word lines of the first memory cell array.

Abstract: A surface micro-machined sensor uses a pedestal in a cavity to support a flexible structure and reduce the span of the flexible structure. The reduced span per sense area allows larger sensor areas without permitting forces to permanently deform the flexible structure or cause the structure to touch an opposite wall of the cavity. The flexible structure bonded to the pedestal and an elevated region surrounding the pedestal defines a cavity between the flexible membrane and a lower plane region. Active regions can be formed in the lower plane region for capacitors or transistors. A pedestal can be of various shapes including a circular, ovoid, rectangular or polygonal shape. The lower plane region can be of various shapes including a ring or donut shape, ovoid, rectangular or polygonal shape with an inner dimension corresponding to the outer dimension of the pedestal. The elevated region can be of various shapes with an inner dimension corresponding to the outer dimension of the lower plane region.

Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of sub-arrays. The number of memory cells per bit line in at least one of the sub-arrays differs from the number of memory cells per bit line in other sub-arrays. When the sense amplifiers can accommodate a bit line loading of (2M+2M/N) memory cells per bit line, the size and bit line loading of one of more of the sub-arrays can be increased. This can provide sub-arrays of different sizes and can reduce the number of the sub-arrays and the number of the sense amplifier regions. Accordingly, the chip efficiency is improved. Maximum current for sensing during simultaneous accesses of multiple arrays can access two sub-arrays with different bit line loadings and avoid simultaneously accessing two sub-arrays having high bit-line loadings.

Abstract: A method of controlling thicknesses of thin film layers in manufacturing semiconductor devices begins with loading monitoring wafers in a thin film forming apparatus. The apparatus has multiple film formation zones, and one of the zones is a reference zone. After forming thin films on the monitoring wafers, thicknesses of the thin films formed on the monitoring wafers are measured. Then, process time and process temperatures are adjusted so that the thicknesses of films are the same as a target film thickness. Finally, thin films are formed on semiconductor wafers using the adjusted process time and temperatures.

Abstract: In accordance with an embodiment of the present invention, a method for manufacturing a semiconductor package of a center pad type device includes: attaching a semiconductor chip to a tape wiring substrate where the chip has bonding pads along a center line of its active surface and the substrate has multiple beam leads; interposing an elastomer between the semiconductor chip and the tape wiring substrate; bonding the beam leads to the respective bonding pads exposed through an opening of the elastomer; and encapsulating the opening and a perimeter of the semiconductor chip with a liquid encapsulant. The method may use a cover film. When the cover film is used, the encapsulation can be done in two ways. In one way, an encapsulant is dispensed on a portion of tape wiring substrate that is close to one end of the opening of the elastomer. The encapsulant is then dispensed along a perimeter of the semiconductor chip.

Abstract: A semiconductor memory device has a sub word line driver structure and includes a main word line decoder driver, an address programming circuit, and a redundant main word line decoder driver. When row address bit signals are input, the main word line decoder driver drives a main word line corresponding to the row address bit signals regardless of a row replacement with redundant rows. If the row address bit signals correspond to programmed defective row address bit signals, the address programming circuit generates a redundant row select signal, in response to which the activated main word line is deactivated and a redundant main word line is activated. According to the redundant row replacement scheme of the present invention, access time is reduced without an increase of a layout area.

Abstract: An inductor includes a semiconductor substrate, pairs of pads formed on the semiconductor substrate at predetermined intervals with the pads in a pair spaced apart a predetermined distance, bonding wires connect the pads constituting the corresponding pairs of pads, and metal lines connect pads among the pairs to other pads to form a current path for the inductor. Since the inductor uses bonding wire which has low resistance and can reduce the contact area with chips, the inductor has few parasitic components and a high quality factor in nearly all frequency regions.

Abstract: A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. The scheduler issues operations to execution units for parallel pipelined execution, selects and provides operands as required for execution, and acts as a reorder buffer keeping the results of operations until the results can be safely committed. The scheduler is tightly coupled to execution pipelines and provides a large parallel path for initial operation stages which minimize pipeline bottlenecks and hold ups into and out of the execution units. The scheduler monitors the entries to determine when all operands required for execution of an operation are available and provides required operands to the execution units. The operands selected can be from a register file, a scheduler entry, or an execution unit.

Abstract: A redundancy circuit is capable of repeatedly replacing a defective cell with redundant cells. The redundancy circuit is in a semiconductor memory device that includes memory cells and redundant cells in a memory array. The redundancy circuit includes first and second fuse blocks. The first fuse block has a first main fuse and generates a first redundancy signal according to whether the first main fuse is cut. The first redundancy signal indicates whether there is a defective memory cell for the redundancy circuit to replace. The second fuse block has a second main fuse and generates a second redundancy signal according to whether the second main fuse is cut. The second redundancy signal can stop the replacement of the defective cell with the redundant cell when the redundant cell is defective. When the replacement of the defective cell with the redundant cell is stopped, the defective cell is replaced by another redundant cell.

Abstract: A peanut combine having a header for lifting peanut laden vines off the ground, an auger for distributing the peanut laden vines, a series of picking or thrashing cylinders for thrashing the peanut laden vines and a series of separator cylinders for removing the peanuts from the peanut laden vines. The separator cylinders include fingers which propel the vines and which rotate at a variable flailing speed. The fingers include tips which vary in angle with respect to the path which the fingers define as they rotate on the separator cylinders.

Abstract: A synchronous motor is divulged whose direction of rotation may be chosen, comprising a rotor with permanent magnet and a stator with homopolar field, including a winding fed with an AC voltage. In response to a stopping order, a circuit controls the switch for opening the connection of the winding when the voltage is decreasing in absolute value or is cancelled out and stores the sign of its slope at the time of opening. The circuit controls the switch for closing the connection when the voltage is cancelled out or is increasing in absolute value, with a sign slope identical to, respectively opposite, the stored sign, in accordance with an order for setting in rotation in a direction identical to, respectively opposite, the preceding direction of rotation.