Abstract: A dynamically controlled timing signal generator includes a source of a controlled current, a timing signal generating circuit coupled to the controlled current source for generating the timing signal, and a feedback circuit coupled to the controlled current source for controlling the controlled current source to produce a desired controlled current.

Abstract: A method for compressing and expanding source image representative data is disclosed. The method for compressing rasterized source image representative data comprises the following steps. The rasterized source image representative data is partitioned into a first plurality of sections each containing only blank lines, and a second plurality of sections each containing non-blank image representative data. Each section in the first plurality of sections is represented by a respective blank-line codeword. Each section in the second plurality of sections is further partitioned into a plurality of blocks, each having L lines of P pixels and a pattern. For each partitioned block, one of a plurality V of code vectors, each having L lines of P pixels and a predetermined pattern which most closely matches the pattern of the partitioned block, is selected. Each partitioned block is represented by a respective non-blank codeword representing the selected one of the plurality of code vectors.

Abstract: A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device Lo the output terminal.

Abstract: A clock distribution system in a reliable electronic system includes a predetermined number of clock signal load circuits, each having a clock signal input terminal. A first clock signal generator has the same predetermined number of clock signal output terminals coupled to the clock signal input terminals of the clock signal load circuits. A second clock signal generator also has the same predetermined number of clock signal output terminals which are also coupled to the clock signal input terminals of the clock signal load circuits.

Abstract: A peripheral device interface is coupled between a computer system bus and a peripheral bus. The peripheral device bus includes a signal line which can be configured in either a single-ended or a differential configuration. A peripheral controller is coupled to the computer system bus. A single-ended signal line interface circuit is coupled between the peripheral bus signal line and the peripheral controller, and may be selectively enabled in response to a control signal. A differential signal line interface circuit is also coupled between the peripheral bus signal line and the peripheral controller and also may be selectively enabled in response to a control signal. The peripheral controller generates the control signals for the single-ended signal line interface circuit and the differential signal line interface circuit.

Abstract: A disk drive controller includes a memory for storing a plurality of blocks each having a predetermined size, and a parity engine. The parity engine includes a data buffer RAM for storing a block having the predetermined size. A function circuit has a first input terminal coupled to the disk drive controller memory, a second input terminal coupled to the output of the data buffer RAM, and an output terminal coupled to the input of the data buffer RAM. A command circuit, conditions the function circuit and the data buffer RAM to operate in a first operating mode to retrieve a block from the disk drive controller memory and store it in the data buffer RAM, and in a second operating mode to calculate the exclusive-OR (XOR) of a block from the disk drive controller memory with a block from the data buffer RAM and store the result in the data buffer RAM.

Abstract: A method and apparatus is disclosed for reliably storing data to be written to a peripheral device subsystem. The method disclosed includes the following steps. A first peripheral device controller, which includes a cache memory, receives write data from a central processor, stores it in its cache memory, and transmits a copy of it to a second peripheral device controller via a communications path. The second controller, which also includes a cache memory, stores the copy of the write data transmitted to it in its cache memory. Meanwhile the first controller processes the write data. In the event the first controller fails, the second controller processes the write data stored in its cache memory. The apparatus disclosed includes a central processor which generates write data. A first peripheral device controller, which includes a cache memory, is coupled to the central processor.

Abstract: A nuclear or x-ray detector which utilizes Compton double-scattering of photons by radiation particles, followed by photoelectron absorption, to reconstruct the energy and direction of such particles.

Abstract: A peripheral device capable of replacing resident microcode with new microcode by download by an application program is disclosed. The disclosed peripheral device comprises a non-volatile memory containing the resident microcode. Further circuitry is responsive to the application program for receiving peripheral device commands. A resident processor, which is coupled to the non-volatile memory and the receiving circuitry, is responsive to the resident microcode, and includes a detector for a received initiator peripheral device command. The resident processor also includes a detector for a transfer disk drive command, which includes the new microcode, and which is received while the disk drive is in a waiting state.

Abstract: A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device to the output terminal.

Abstract: A system bus 12 for an information processing system 10 includes a first group of signal lines 16 whereon command/ID information is time multiplexed with data, and a second group of signal lines 14 for conveying address information. During a first bus cycle command/ID information is presented on the first group of signal lines while the address is presented on the second group of signal lines. During a subsequent bus cycle, and for a data write or data return operation, the first group of signal lines conveys data. Other bus connections, such as cache memories, are thus apprised of the address a full bus cycle before the data is presented thereby providing the bus connections with sufficient time to decode and otherwise operate on the bus information. Multiple word data returns from a system memory are characterized as having the address associated with a particular word of data presented in the immediately prior bus cycle, facilitating the pipelining of data and address information through the system bus.

Abstract: An information processing system includes a first data processing device 10 and a second data processing device 12 each of which is capable of independent instruction execution during instruction cycles having a period which is a multiple of a periodic unit clock signal period. The devices are disclosed to be an arithmetic unit and a central processor which are coupled together by an interface 14. Each of the data processing devices include a clock generation device 180 having an input coupled to the unit clock signal for generating an associated instruction cycle clock signal which has a period which is a multiple of the unit clock signal period. The clock generation device is further operable for suspending the generation of the instruction cycle clock signal and for beginning a next instruction cycle clock signal in synchronism with a transition of the unit clock signal.

Abstract: An invalid walker is disclosed which includes two vertical members with a horizontal support near the top of the walker. The vertical members are relatively coplanar near the bottom of the walker.

Abstract: A computer system having a digitizing tablet overlaying the display screen. The tablet serves as a user's primary input device. Various features of the system make it possible for the user to run and interact with standard programs designed for keystroke and mouse input and not designed for use with a tablet. In addition to the main processor, on which the user's programs are executed, there is an interface processor. In addition to a standard display buffer, there is an ink plane buffer for interface display data that is combined with the data from the standard display buffer on a pixel-by-pixel basis according to data from a mask plane buffer. The interface processor manages input from the tablet, presents feedback to the user by means of the ink and mask planes, and provides keystroke and mouse data to the main processor as if from a standard keyboard controller. The interface processor presents the user with a collection of simulated devices, including standard devices such as a keyboard and a mouse.

Abstract: A computer operated controller for controlling and/or monitoring a physical object and a logical abstraction related to the physical object is disclosed. The controller comprises a physical object entity representing the physical object. The physical object entity includes storage for physical-object-specific data and a script describing the behavior of the physical object. The controller further comprises a logical abstraction entity representing the logical abstraction. The logical abstraction entity further includes storage for logical-abstraction-specific data and a script describing the behavior of the logical abstraction.

Abstract: A ringing signal generator includes a low power signal generator for generating a relatively low power signal representing a ringing signal, a bipolar pulse generator for generating a series of bipolar pulses having widths representing the amplitude of the low power signal, wherein adjoining pulses have opposite polarities, and a high power ringing signal generator for producing a high power ringing signal in response to the series of bipolar pulses. An analog sine wave signal is superimposed upon a DC bias signal to produce the low power signal.

Abstract: A low offset transconductance amplifier, in an analog electronic cochlea comprises: first and second differentially connected input transistors; an input current source transistor; an output current sink transistor; first means for inducing a current in the output current source transistor in response to the first input transistor; and second means, for inducing a current in the output current sink transistor in response to the second input transistor, including a cascode transistor.

Abstract: With the switching node at least one coupling element is associated which has a number n of input lines and n output lines optionally connectible to the input lines via a space switch with a buffer store being assigned to the input lines in which k data packets occurring sequentially on the particular input line are storable before being routed further to the output lines indicated by the address signals contained in the particular data packet. The buffer stores have each a plurality m.ltoreq.k output terminals via which simultaneously m data packets stored in the particular buffer store and to be routed further to m different output lines are suppliable to a space switch having m.times.n input terminals and n output terminals.

Abstract: An adaptive compensator circuit is provided which includes a first echo compensator, responsive to data signals from the transmitter, for providing a first compensation signal for compensating an echo signal component which is linearly related to the digital signals to be transmitted. A second echo compensator, responsive to both the first compensation signal and the corrected received signal provides a second compensation signal for compensating the nonlinear echo signal component. An adder, responsive to the first and second echo compensation signals, provides a summed compensation signal. The data signals from the receiver are corrected by means of the summed compensation signal. In another embodiment, the second echo compensator is responsive to both the corrected received signal and the current symbol being transmitted by the transmitter and the (N-1) preceding symbols.