Abstract: An upgradeable/downgradeable data processing system capable of operating with different types of central processing units (CPU). The system has a first socket for registration of a first CPU and a second socket for registration of a second CPU. Means are provided for preventing possible signal contention between the first and second CPU, and for synchronizing clocks for operating a CPU with the system clock. Means are also provided for interfacing with a coprocessor associated with the different types of CPU as well as for adjusting the signals to and from the CPU to the signal width of the system.