Abstract: A sensor includes a sensor stack and a layer of high resistivity material having a precursor within the sensor stack. When a current is applied at the precursor, a current confining path is formed through the layer of high resistivity material at the precursor. The shape of the current confining path is adjustable by adjusting a thickness of the layer of high resistivity material.

Abstract: A data communication system having improved error correction and detection capabilities includes an encoder which converts each input word containing three binary message bits to an eight-bit binary code vector which contains exactly four "1's" and four "0's", and thus has a fixed "weight" of 4. In addition, the same symbol (either a "1" or "0") is consecutively repeated in the code vector no more than two times. The code vector is transmitted from a transmitter to a receiver, and the eight-bit received vector is decoded by a decoder to produce an output word containing three message bits. The decoder detects errors in received vectors by checking the weight of the received vector, by checking syndrome based upon predetermined combinations of bits of the received vector, and by performing a parity check on two selected bits of the received vector which should be unequal.

Abstract: A frequency shift keyed (FSK) data transmission system utilizes existing power lines to transmit data by superimposing a high frequency FSK signal on the power line carrier. A transmitter includes a phase locked loop which is locked on the power line carrier frequency and which synthesizes the FSK signal and a timing signal which defines the data rate of the transmitter. As each bit is transmitted, an oscillator control signal either speeds up or slows down the loop oscillator temporarily to produce the FSK signal. A receiver demodulates the data transmission from the power line by separating a power line carrier frequency component and a FSK signal component. The receiver includes a phase locked loop which locks onto the power line carrier frequency and which synthesizes a reference frequency and a timing signal which defines the data rate of the receiver.

Abstract: A phase locked loop provides limited phase correction when in lock in order to minimize the effects of noise in the periodic input signal to which the loop is locked. The phase locked loop includes a voltage controlled oscillator (VCO), a timing generation divider, a phase detector, a lock detector and an oscillator control circuit. The phase detector provides an output based upon the phase difference between rising edges of the input signal and a loop synthesized signal which is derived by the divider from an oscillator output signal. A window signal, which begins slightly before and ends slightly after an anticipated rising edge of the input signal, is also derived from the oscillator output signal. The lock detector provides a lock detect signal which indicates whether the loop is in lock. The oscillator control circuit provides an oscillator control voltage based upon the phase detector output signal, the window signal, and the lock detect signal.

Abstract: A CMOS window detector provides outputs which indicate whether an input voltage is within a voltage "window". The window detector includes a bias circuit and first and second inverter circuits. A bias current is established by the bias circuit as a function of a reference voltage. The first and second inverter circuits each include a current mirror field effect transistor (FET) and a current control FET connected in a series current path. The current mirror FETs are connected to the bias circuit to provide two different mirror currents. The mirror currents are a function of the bias current and the current mirror FET channel shape factors. The input voltage signal is applied to the gates of the current control FETs of the first and second inverters. The window voltage level of each inverter circuit is independent of the other inverter circuit and is determined as a function of the mirror current and channel shape factor of the current control FET.

Abstract: A power up reset pulse generator circuit provides a reset pulse to initialize the states of logic elements in a low power field effect transistor (FET) integrated circuit. The reset pulse generator includes a pair of P-channel enhancement FETs and a first capacitor connected in a series charging path between V.sub.DD and V.sub.SS power supply terminals of the integrated circuit. A second capacitor, and a pair of N-channel enhancement FETs are connected in a second series charging path between the V.sub.DD and V.sub.SS terminals. The second capacitor is connected between the V.sub.DD terminal and an output node, at which the reset pulse is provided. Before power is applied, the first and second capacitors are uncharged and all four FETs are off. When power is applied and the potential between V.sub.DD and V.sub.SS terminals exceeds twice the P-channel threshold voltage, the P-channel FETs turn on, thereby allowing the first capacitor to begin charging. In the meantime, the voltage at the output has followed V.

Abstract: A CMOS window detector provides an output signal which indicates the relationship of an input signal to a voltage "window" as a function of the previous output signal. The window detector includes first and second current source circuits and first and second inverter circuits. A bias current is established in each current source circuit as a function of a different reference voltage. The first and second inverter circuits each include a current mirror field effect transistor (FET) and a current control FET connected in a series current path. The current mirror FET of each inverter circuit is connected to its respective current source circuit and establishes a current in the inverter current path equal in magnitude to its respective bias current. The input signal is applied to the gates of the current control FETs. Each current control FET changes conductivity state when the input signal reaches the reference voltage level used to establish the respective inverter current flow.

Abstract: A frequency shift key receiver includes a phase velocity sign detector which detects whether a FSK modulated input signal has a frequency (f.sub.FSK) which is greater than or less than a reference frequency (f.sub.0) of a REF signal. The phase velocity sign detector includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The phase velocity sign detector includes a sequence detector which provides an output signal indicating whether the FSK signal has a frequency greater than or less than the REF signal based upon the sequence of the code from the sequence generator. The phase velocity sign detector demodulates the FSK signal in the digital domain using circuitry which is completely integrable on a monolithic integrated circuit chip.

Abstract: Temperature variation of the input bias current of a monolithic integrated circuit junction field-effect transistor (JFET) is provided by a compensation diode formed concurrently with the JFET in the monolithic integrated circuit. The compensation diode has a first region which is formed concurrently with the channel region of the JFET, and a second region which is formed concurrently with the gate region of the JFET. The areas of the first region and the channel region are equal. In addition, the area of the junction formed by the first and second regions of the compensating diode is equal to the area of the junction formed by the gate and channel regions of the JFET. The first region of the compensation diode is electrically connected to the gate region of the JFET so that reverse leakage current of the compensation diode compensates and tends to cancel the reverse leakage current of the gate-channel junction of the JFET.

Abstract: A frequency shift key demodulator produces an output data stream based upon whether a FSK modulated input signal has a frequency (f.sub.FSK) which is greater than or less than a reference frequency (f.sub.0) of a reference (REF) signal. The demodulator includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The demodulator also includes first and second sequence detectors, first and second integrating shift registers, and a decision circuit. The first sequence detector provides an output signal to the first shift register indicating that the FSK signal has a frequency less than the REF signal based upon detection of a first predetermined sequence of the code from the sequence generator.

Abstract: A voltage controlled current source provides a load current through a load impedance which is a function of an input voltage and is independent of the impedance value of the load impedance. The voltage controlled current source includes a high input impedance unity gain instrumentation amplifier and a resistor connected in series with the load impedance so that current flows through the resistor and the load impedance. The instrumentation amplifier receives the input voltage at its inverting input and receives a load voltage representing the voltage across the load impedance produced by the load current at its noninverting input. The instrumentation amplifier subtracts the input voltage at the inverting input from the load voltage at the noninverting input and multiplies by a gain of one to produce an output voltage at its output. The resistor and the load impedance are connected in series between the output of the amplifier and a reference voltage (e.g.

Abstract: A threshold voltage control circuit controls the threshold voltages of one or more field-effect transistors (FETs) of an integrated circuit. The threshold voltage control circuit includes a reference (FET) which is electrically connected to the other FETs so that the threshold voltage of the reference FET determines the threshold voltages of the other FETs. A bias voltage is applied to a gate of the reference FET and a current path is established between first and second supply terminals. This current path includes the drain and source of the reference FET. The current flowing in the current path is a function of the bias voltage applied to the gate of the reference FET and the threshold voltage of the reference FET. A high gain, high input impedance amplifier is connected to the current path and provides a threshold control signal to the reference FET (and the other FETs) which is a function of the current in the current path.

Abstract: An improved Dewar assembly for infrared detectors is disclosed. Vacuum tight feed-throughs are partially embedded in the inner flask with exposed portions on both sides of a vacuum seal.

Abstract: A mercury cadmium telluride photodiode includes an n-type mercury cadmium telluride body with an accumulation layer proximate a first surface of the body. A p-type region is formed in the body at the first surface so that the n-type accumulation layer surrounds the p-type region at the first surface.

Abstract: A hybrid mosaic IR/CCD focal plane structure is fabricated using planar thin film interconnects. Rows of detectors are formed on an integrated circuit substrate so that the rows of detectors are adjacent to rows of electrical contacts on the integrated circuit. Contact pads are plated onto the rows of contacts and the regions between adjacent rows of detectors are backfilled with an insulating material. The insulating material is then lapped to expose the contact pads and to form an essentially coplanar surface with the detectors. Thin film interconnects are formed over the coplanar surface between the exposed contact pads and detectors in the adjacent row.

Abstract: A hybrid mosaic IR/CCD focal plane structure has high detector element packing densities which may be achieved using cost effective planar processing technology. The focal plane structure preferably includes an insulator layer over a silicon substrate which contains integrated circuit CCD signal processing circuitry. A mosaic photovoltaic (Hg,Cd)Te detector array is fabricated on the insulator layer. The photosignals from the detector array are coupled to the CCD circuitry by thin film electrical interconnects together with contact pads which extend through the insulator layer and are exposed at the surface of the insulator layer.

Abstract: A hybrid mosaic IR/CCD focal plane structure is fabricated on a silicon substrate which contains integrated circuit CCD signal processing circuitry. Contact pads are formed which are connected to the signal processing circuitry and which extend above the surface of the silicon substrate. An insulator layer is formed which covers the substrate and the contact pads. The insulator layer is then lapped to form an essentially planar surface with the contact pads exposed. A mosaic detector array is fabricated on the insulator layer, and thin film electrical interconnects are formed from the detectors to the exposed contact pads to couple the photosignals from the detector array to the CCD circuitry.

Abstract: A pyroelectric detector as formed by parylene C polymer film.

Abstract: An ultraviolet sensitive photodiode is formed in a body of first conductivity type GaP. A region of second conductivity type with a graded impurity distribution is formed in the body, and a thin layer (preferably about 100A to 300A) is then removed from the front surface of the body. The removal of the thin layer significantly enhances the performance of the UV sensitive photodiode.

Abstract: A hybrid mosaic IR/CCD focal plane structure is fabricated using planar thin film interconnects. Rows of detectors are formed on an integrated circuit substrate so that the rows of detectors are adjacent to rows of electrical contacts on the integrated circuit. Contact pads are plated onto the rows of contacts and the regions between adjacent rows of detectors are backfilled with an insulating material. The insulating material is then lapped to expose the contact pads and to form an essentially coplanar surface with the detectors. Thin film interconnects are formed over the coplanar surface between the exposed contact pads and detectors in the adjacent row.