Abstract: A neural integrated circuit, comprising a synaptic coefficient memory, a neuron state memory, resolving means and learning means which simultaneously operate in parallel on each of the synaptic coefficients in order to determine new synaptic coefficients. The learning means comprise means for performing a learning function on the states Vj of input neurons and on a correction element Si which is associated with each output neuron, and also comprise incrementation/decrementation elements which determine the new synaptic coefficients in parallel. The learning functions may be formed by logic AND-gates and exclusive-OR gates. The integrated circuit is used in a neural network system comprising a processing device.

Abstract: A processing module for performing an operation of the type B=a.X+T in which B, X and T are high value integers, and a is an operand having a format restricted to m bits, in sequences constituted from computing steps consisting in combining the operand a with operands x.sub.i and t.sub.i, of restricted format, extracted from the data X and T, at the rank of significance i and in storing a partial result b.sub.i of the same significance rank, this processing module including a static multiplier and two adders and a resistor for storing and recycling the most significant portion of a previous computing step. The processing module includes k inputs for operands a (l . . . k) of successive ranks, for successively applying, in work cycles k steps the said operands a (l . . .

Abstract: Teletext decoder including an error detection and correction circuit in which the detection and correction of bit errors is effected in a serially manner in Hamming bytes. The teletext decoder includes selection means for selecting predetermined bits from the received bytes, modulo-2 accumulators for generating a syndrome word which indicates the presence and position of bit errors, decoding means for generating a correction value and correction means for correcting faulty data bits during the serial transfer. The error detection and correction circuit can also be used with other data communication systems as well as with digital storage means.

Abstract: A nonvolatile storage device is provided with at least one stacked poly gate structure formed on the substrate and disposed between a first trench and a second trench. The trenches each having two walls. A first doped area having a first conductivity type extending along the wall of the first trench and a second doped area having a second conductivity type extending along the wall of the second trench. The first doped area and the second doped area having heights greater than widths, the heights being parallel to the trench walls and the widths being perpendicular thereto. The trench walls are lined with a metal silicide to decrease resistivity.

Abstract: A stacked floating-gate field-effect transistor ("FET") structure suitable for memory cells in a nonvolatile memory is fabricated according to a process in which a floating-gate layer is formed on a semiconductor substrate (30), oxide (42) is formed along the sidewalls (35) of the floating gate (18) extending in the channel-length direction, and an oxide-nitride-oxide ("ONO") composite layer (44) is formed along the top of the structure, including the floating gate and the sidewall oxide. The ONO composite layer and the sidewall oxide act as an isolation dielectric between the floating gate and a control gate (20) formed on top of the ONO layer.

Abstract: A control circuit comprising a thyristor and a feedback circuit formed by an inductance and a generator for producing electrical energy in response to a luminous event. The feedback circuit controls the conducting or cut-off state of the thyristor by the fact that a trigger-gate of the thyristor is connected to a terminal of the generator having a polarity cutting off the thyristor when the generator is illuminated. The thyristor is switched on in response to an energy stored in the inductance, which energy is caused by a sudden discontinuity of the luminous event.

Abstract: Apparatus and method for insuring data cache content integrity among parallel processors is provided. Each processor has a data cache to store intermediate calculations. The data cache of each processor is synchronized with each other through the use of synchronization intervals. During entry of a synchronization interval, modified data variables contained in an individual cache are written back to a shared memory. The unmodified data contained in a data cache is flushed from memory. During exiting of a synchronization interval, data variables which were not modified since entry into the synchronization interval are also flushed. By retaining modified data cache values in the individual processors which computed the modified values, unnecessary access to shared memory is avoided.

Abstract: High speed and high drive BiCMOS buffers, inverters, and gates receiving synchronous differential inputs are provided having at least two npn bipolar transistors and at least one nMOS transistor. The first bipolar transistor has a base receiving a noninverting input, a collector coupled to the high voltage rail, and an emitter coupled to the circuit output. In several embodiments, the second bipolar transistor has its collector coupled to the emitter of the first bipolar transistor, its emitter coupled to ground, and its base coupled to the source of an nMOS transistor which is receiving the inverting input at its gate. In these embodiments, the output is taken from the emitter of the first bipolar transistor and the collector of the second bipolar transistor with the first bipolar transistor pulling up when the input is high, and the second bipolar transistor pulling down when the input is low.

Abstract: In an integrated circuit random access memory internally a xn (n>1) organization is realized, that externally translates to a x1 organization. The n data bits read in parallel are successively and selectively activated and after multiplexing buffered in sequence. Upon buffering but not yet outputting the last data bit of a read address, the next read address may be applied. In this way a multi-address page mode or cross address nibble mode is realized. For writing, a resettable data input delay buffer maintains sufficient margin for both Tdh and Tdv in that any old data is deactivated before new data appears. In this way an equalization pulse no longer is required.

Abstract: In a driver circuit, high- and low-impedance drive means (26 and 28 respectively) operate in parallel to effect a desired output transition. Adaptive control means 32 respond to a threshold value of the output signal (VO) and turn off the low-impedance drive means in the course of the output transition. The low initial output impedance of the driver circuit effects rapid charging of a line capacitance CL, while toward the end of the output transition the higher output impedance of the driver circuit more closely matches the input impedance ZL of a load circuit. This higher impedance dampens ringing and thereby reduces induced supply line noise which is conventionally associated with high-speed driver circuits.

Abstract: A static RAM has for each row of cells a bit line and an inverted bit line. For allowing the current data being driven to each cell to be instantaneously stopped and for allowing the (inverted) bit line to go back to a safe non-writing condition two resettable delay chains are provided between a buffering element that has mutually logically inverse data outputs. Each chain has a first sequence of alternating inverter gate series feeding a second sequence of one or more inverters. At the end of a write cycle the gates are reset in parallel, thus shortening the delay to about that of the second sequence only. In this way operating margins are retained.

Abstract: An ideographic teletext transmission system based on the World System Teletext specification in which ideograms are displayed in the space of two character positions in each of three display rows, the ideogram code being defined by the corresponding bytes in one, e.g. the first, of the transmission packets corresponding to the three display rows and the corresponding bytes in another of the transmission packets corresponding to the three display rows being used to define an attribute code thereby affording a non-spacing attribute facility.

Abstract: Classification method implemented in a layered neural network, comprising learning steps during which at least one layer is constructed by the addition of the successive neurons necessary for operating, by successive dichotomies, a classification of examples distributed over classes. In order to create at least one layer starting with a group of examples distributed over more than two classes, each successive neuron tends to distinguish its input data according to two predetermined sub-groups of classes peculiar to the said neuron according to a principal components analysis of the distribution of the said input data subjected to the learning of the neuron of the layer in question.

Abstract: Maneuvers of a controlled vehicle, such as a car, traveling at moderate to high speeds are planned by propagating cost waves in a configuration space using two search strategies referred to as budding and differential budding. Control is achieved by monitoring properties of the controlled vehicle and adjusting control parameters to achieve motion relative to a frame of reference. The frame of reference may change before the transformation to configuration space occurs. The method transforms goals, obstacles, and the position of the controlled vehicle in task space to a configuration space based on the position of these objects relative to a moving frame of reference. The method also determines a local neighborhood of possible motions based on the control capabilities of the vehicle. In one embodiment, the controlled parameters are time derivatives of the monitored properties. A variation of the method provides for the parallel computation of the configuration space.

Abstract: Classification procedure implemented in a tree-like neural network which, in the course of learning steps, determines with the aid of a tree-like structure the number of neurons and their synaptic coefficients required for the processing of problems of classification of multi-class examples. Each neuron tends to distinguish, from the examples, two groups of examples approximating as well as possible to a division into two predetermined groups of classes. This division can be obtained through a principal component analysis of the distribution of examples. The neural network comprises a directory of addresses of successor neurons which is loaded in learning mode then read in exploitation mode. A memory stores example classes associated with the ends of the branches of the tree.

Abstract: A process for fabricating a compact bipolar transistor structure is disclosed which eliminates the need for a field oxide isolation region between the collector contact region and emitter of the transistor. An island of non-monocrystalline silicon is formed on top of the transistor structure partially covering the base and collector contact regions. Ribbons of non-insulating material are formed along the sidewalls of the island. The ribbon over the base region is employed to form a narrow emitter region with an annealing step that drives dopant from the ribbon or island into the portion of the base region below the ribbon. An insulating layer is disposed between the transistor structure and the island and ribbon over the collector contact region to insulate the emitter from the collector. Insulating sidewall spacers are formed next to the sidewall ribbons to insulate silicide regions grown over the base region, island and collector contact region for the three transistor contacts.

Abstract: A "correct page header received" (CPHR) flip-flop (3) is set by the page header of a required teletext page and reset by the next following page header, a "page end" flip-flop (15) generates a page end output (17) in response to the receipt of the next following page header, a "row received" flip-flop (11) detects at least one row of the required teletext page, a gate (14) inhibits the generation of an end of page output (21) for a predetermined period, typically corresponding to three field intervals, and an AND gate (18) further inhibits the generation of an end of page output (21) if there has been a subsequent detection of a further page header of the required teletext page within the predetermined period.