Patents Represented by Attorney David T. Caplan

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  • Synthetic CMOS static logic gates
    Patent number: 4649296
    Abstract: A multi-input CMOS integrated circuit gate is made with fewer PFETs connected between the source voltage and the output node than there are inputs. In many cases only a single PFET is employed. The inputs are applied through a logic network connected to the gate of the remaining PFET. The gate exhibits reduced parasitic capacitance, better PFET-NFET size ratios, and higher speeds.
    Type: Grant
    Filed: July 13, 1984
    Date of Patent: March 10, 1987
    Assignee: AT&T Bell Laboratories
    Inventor: Masakazu Shoji