Abstract: A driver circuit for slope-controlled pulsed switching of a load having a MOS switching transistor switching the load and a control loop with an amplifier having an amplifier input coupled with a switch control pulse source, an amplifier output connected with the gate of the MOS switching transistor, and a feedback capacitor. The driver circuit also includes a switchable current mirror circuit with a current mirror transistor formed by the MOS switching transistor and a diode transistor wired as a current mirror diode, a connection point between the diode transistor and the gate of the MOS switching transistor being connected with the amplifier output. A timer circuit is supplied on the input side with the switch control pulses from the switch control pulse source, and switches the diode transistor into a conductive state for essentially the duration of each switch control pulse edge and otherwise into a nonconductive state.

Abstract: An integrated circuit device includes operational circuitry, for example, in the form of a memory for carrying out operations of the integrated circuit device. Additionally, at least one peripheral circuit is connected to the operational circuitry for carrying out at least one function in respect of the operational circuitry. Input means are provided to permit the input of command data in a normal mode of operation and to permit the input of test data in a test mode of operation. Control circuitry has an input to receive command data from the input means. The control circuitry is arranged to generate, in response to the command data, control signals to control at least one of the peripheral circuits in the normal mode of operation. A control bus is connected between the control circuitry and the peripheral circuits and is arranged to carry control signals from the control circuitry to at least one peripheral circuit.

Abstract: A invention provides a transformer for use in integrated circuits, comprising four layers of conductive lines, separated from each other by first, second and third insulating layers. First conductive vias traverse the second insulating layer to connect said second and third pluralities of conducting lines, to form a first winding. Second conductive vias traverse the first, second and third insulating layers to connect said first and fourth pluralities of conducting lines to form a second winding, about and approximately concentric with said first winding.

Abstract: The invention relates to a driving circuit for row decoding which is also useful in non-volatile memory devices of the multi-level Flash type and the multi-level EPROM type and allows the overall capacitive loads as seen from the program voltage generator and the read/verify voltage generator, to be drastically reduced without involving segmentation of the decoding circuit.

Abstract: To manufacture integrated semiconductor devices comprising chemoresistive gas microsensors, a semiconductor material body is first formed, on the semiconductor material body are successively formed, reciprocally superimposed, a sacrificial region of metallic material, formed at the same time and on the same level as metallic connection regions for the sensor, a heater element, electrically and physically separated from the sacrificial region and a gas sensitive element, electrically and physically separated from the heater element; openings are formed laterally with respect to the heater element and to the gas sensitive element, which extend as far as the sacrificial region and through which the sacrificial region is removed at the end of the manufacturing process.

Abstract: An electrical switching device including a switch having a control terminal, a control circuit coupled between a first voltage source terminal and a second voltage source terminal and a control signal input coupled to receive a binary switching control signal.

Abstract: A device for the selection of address words each having n bit locations and serving for addressing m different receiving locations of a digital communication module, in at least one of the receiving locations, including a digital acceptance module through which address words can be selected. The device has an address word segmenting module through which each address word received by the receiving location can be subdivided into s address word segments with b segment bit locations each, wherein b=n/s and n is an integral multiple of s. The device further has z digital segment filters whose inputs can each be fed with an address word segment, with each segment filter having the function of examining one address word segment each with respect to conformity with a predetermined segment bit pattern, and a filter output signal being available at the output of the respective segment filter, which in accordance with the examination result is either a conformity signal or a non-conformity signal.

Abstract: The present invention relates to a radio receiver, particularly to a receiver for use in single-frequency applications, such as GPS, and to a frequency generator, which may be used in such a radio receiver, or elsewhere. The frequency generator comprises a tuned circuit connected between the emitter of the transistor and ground, such that a voltage signal at the basic frequency appears on the emitter terminal of the transistor. This arrangement has the advantage that the two frequencies appear on separate ports, and provides a radio receiver including radio receiver circuitry for connection to digital signal processing circuitry, reducing the complexity of the overall circuit. Additionally, there is a radio receiver wherein separate first and second local oscillator signals are generated from the terminal of s single transistor, avoiding the need for cascade multiplication stages, again reducing the size and complexity of the overall circuit.

Abstract: The invention relates to a method of and an apparatus for controlling a plurality of mutually communicating actuators, each of the actuators having at least one signal sensor for determining the state of the actuator, with at least one control apparatus generating, in accordance with the state of at least one of the actuators, control signals used for driving controllers of the actuators. In order to avoid overheating of the individual actuators or the control apparatus in case of a large number of actuations by a user, it is provided to determine the temperature of the actuators and the control apparatus cooperating with the actuators and, in case a predetermined temperature threshold value is exceeded in an actuator or the control apparatus, to generate a control signal for non-driving the controllers of the actuators until the excessive temperature detected drops below the temperature threshold value by a defined temperature value.

Abstract: A programming method for a nonvolatile memory includes the steps of: a) determining a current value of the threshold voltage; b) acquiring a target value of the threshold voltage; c) calculating a first number of gate voltage pulses necessary to take the threshold voltage from the current value to the target value; d) applying a second number of consecutive voltage pulses to the gate terminal of the cell, the second number being correlated to the first number and having a uniformly increasing amplitude; e) then measuring a current value of the threshold voltage; and repeating steps c) to e) until a final threshold value is obtained.

Abstract: A monolithic integrated multiple mode circuit having an output stage, a transfer gate, a control circuit arrangement, and a well contacting region where a well potential may be applied, the multiple mode circuit adapted to be controlled into an output stage mode or an input stage mode by means of control data.

Abstract: A protection circuit for the prevention of program interruptions of electrical equipment controlled on the basis of program step clocks, by too frequent occurrences of non-maskable interrupt signals. This protection circuit comprises a controllable interrupt signal passage circuit which, depending on an output signal of a control signal source, can be controlled to a state permitting the passage of the non-maskable interrupt signal or to a state blocking said signal. The control signal source comprises a clock counter with overflow resetting function, by means of which program step clock pulses can be counted starting from a predetermined initial counting value until a predetermined overflow counting value is reached. The control signal source comprises furthermore an interrupt signal counter the counting value of which can be increased by each non-maskable interrupt event and decreased each time the overflow counting value of the clock counter is reached.

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals and an output for an analog signal. It comprises a current amplification circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference of potential. The converter has drain terminals coupled together and to the input of the amplification circuit, and has control terminals coupleable, under control from the inputs of the plurality, to different references of potential having selected fixed values.

Abstract: A sense amplifier circuit for a semiconductor memory device comprises first current/voltage conversion means for converting a current of a memory cell to be read into a voltage signal, second current voltage/conversion means for converting a reference current into a reference voltage signal, and voltage comparator means for comparing the voltage signal with the reference voltage signal. The sense amplifier circuit comprises capacitive decoupling means for decoupling the voltage signal from the comparator means, and means for providing the capacitive decoupling means with an electric charge suitable for compensating an offset voltage introduced in the voltage signal by an offset current superimposed on the current of the memory cell to be read.

Abstract: A method for locating possible defects on an opaque layer deposited on a production wafer of a semiconductor circuit, consisting in locally radiating an upper surface of the wafer by means of a laser, and detecting the occurrence of a current in a diode constituted by a PN junction placed under the opaque layer to be examined.

Abstract: A non-volatile integrated device having first and second dimensionally different polysilicon gate layers separated by an oxide layer for hot-carrier reliability. More specifically, the oxide and second polysilicon gate layer are selectively etched to form a second gate region over the first polysilicon gate layer that electrically contacts the first polysilicon gate in one direction and is isolated by the oxide in the other direction. Insulating sidewalls are formed over the first polysilicon gate layer regions that are not electrically contacted by the second gate layer to help isolate the second polysilicon gate and form an LDD structure within the substrate for the device.

Abstract: A control circuit adapted to be switched to a standby mode during periods without control requirement and to be repeatedly reset during the standby mode of operation for a short wake-up period each to a full mode of operation. The control circuit comprises a standby oscillator that is operative also in the standby mode and that is adjusted during wake-up periods.

Abstract: The invention refers to a generating circuit for synchronization signals to regulate the read phase of memory cells in electronic devices with an integrated memory on a semiconductor, of the type controlled by a switching of logical states on a left ATD bus and a right ATD bus and comprising a left and a right section inserted between a first and a second voltage reference and connected respectively to the left and the right ATD bus, the sections being connected at the input to a reference-voltage generated and at the output to an ATD generator.

Abstract: A filter circuit adjustably decreases or increases the amplitude of audio signals in a predetermined frequency range. The filter circuit includes a filter module having an RC network with at least one frequency-response-determining RC member whose resistor component R is realized in SC technology. A setting device is connected to the filter module such that its setting determines the frequency response of the SC filter. The setting device renders possible a neutral setting in which the effective audio signal path of the filter circuit circumvents the filter module so that no decrease or increase of the amplitude of individual frequency portions takes place. Furthermore, an audio signal processor comprises at least one audio signal input, at least one audio signal output, and at least one control input.

Abstract: The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.