Abstract: A monolithically integrated signal processing circuit comprising a signal series branch connected between a signal input terminal and a signal output terminal; a reference potential terminal; a series capacitor inserted in serial manner in the signal series branch and having a parasitic capacitance acting like a capacitor that is connected between a first electrode of the series capacitor directed towards the signal input terminal and the reference voltage terminal; and a first parallel capacitor connected between the first electrode of the series capacitor and the reference potential terminal; with the first parallel capacitor being constituted at least in part by the parasitic capacitance.