Abstract: In an ACD system, motivational feedback information, such as the cumulative number of bonus points earned, is displayed on agents' terminal displays. The information is real-time, up-to-date, and substantially continuously displayed. It combines an objective, quantitative measure, such as the number of calls handled, and a subjective, qualitative measure, such as a quality factor representing a supervisor's evaluation of the agents' observed performance in handling calls. Illustratively, the per-call quantitative measure is multipled by an agent's presently-assigned qualitative measure to arrive at the per-call number of bonus points earned by the agent.

Abstract: A shared-buffer-memory-based ATM switching module (FIG. 1) used with ATM cells having a multiplicity of priorities has a plurality of queues (100) for each output port (O-N), one for each cell priority, and handles buffer overflow in a manner fair to all output ports. It initially allows output-port queues (100) to completely consume the buffer memory (12). Thereafter, when an additional incoming cell is received for which there is no room in the buffer memory, the lengths of all of the queues of each output port are individually summed (402) and compared to determine which port has the greatest number of buffered cells (406). A buffered ATM cell is discarded (410) from the lowest-priority non-empty queue of that port (408). The incoming cell is then stored in the memory space vacated by the discarded cell (412).

Abstract: An N+1 sparing strategy for both line circuits and switching nodes of a self-routing 3-stage Benes packet telecommunications network. Line circuits selectively serve either their own telecommunications line or the line normally served by the corresponding line circuit of the preceding row of the switching matrix. A row of spare line circuits and switching nodes is provided. Upon failure of a matrix internal node, line circuits modify packet addresses to reroute packets normally served by the failed node, or nodes below it within the same switching stage, to the next-lower row. Upon failure of a matrix edge node, line circuits of the failed node's row are disabled and line circuits of each row below it commence to serve the lines normally served by the preceding row. Active line circuits also modify packet addresses to reroute packets normally served by the last-stage node of the failed node's row, or rows below it, to the next-lower row.

Abstract: A DMA or communications controller, such as a DMA serial controller, operating under control of, and in cooperation with, a microprocessor together perform the functions of, and hence replace, a bit-mapped display controller, thereby avoiding the cost of the display controller. The microprocessor is programmed to cause the DMA or communications controller to transfer image data to a display, like the display controller. Under the processor's repeated commands, the communications controller transfers data representative of an image from a memory to the display a line of a frame of the image at a time. The processor generates control signals, such as horizontal and vertical sync signals, to cause the display to display the image represented by the transferred data.

Abstract: A wireless-access communications system, such as a CDMA cellular radio-telephone system (FIG. 2), comprises a packet-switched communications network (202, 207, 201) that interconnects cells (base stations; 202) with each other and with the public telephone network (100). Traffic of individual calls is packetized, and packet-bearing frames (300 in FIG. 7) of a plurality of calls are then statistically multiplexed and frame-relayed through the network to yield the high capacity, efficiency, and speed of traffic transport and handoff required for a CDMA cellular system. At each call processing unit (264 in FIG. 5), individual calls are handled by individual service circuits (602 and 612) which perform speech-processing functions such as coding and decoding, tone insertion, and echo cancellation, and packet-to-circuit-switched-PCM traffic conversion.

Abstract: A CDMA cellular radio-telephone system (FIG. 2) has switching systems (201) synchronized to public telephone network (100) timing signals (600), and radio telephones (203) and cell base stations (202) synchronized to a different clock (1000). Transmission delays between the cell base stations and the telephone network are variable. Switching systems include digital communications interfaces (264) to the telephone system, whose connections to the telephone system are synchronized to the telephone system, and whose connections to the cells are nominally also synchronized to the telephone system but whose processor (602) operates for each call within predefined windows (1302, 1402) of phase relationships to the operation of the cell that is handling the call, and occasionally adjusts (FIGS. 13-16) its phase relationships to the operation of the telephone system to achieve and maintain its operation within the predefined windows.

Abstract: An automatic callback arrangement for an automatic call-distribution (ACD) system. The arrangement collects and stores the telephone number from which a call is incoming (ANI), estimates how long the call will have to hold in queue before it is answered, and, if the waiting time exceeds a predetermined maximum, prompts the caller to chosse between holding or receiving a return call if the caller is a valid-account holder. If the caller choses a return call, the arrangement prompts the caller for callback time and time-period. The arrangement then verifies whether the caller is a valid account holder. If so, the arrangement places an outgoing call to the stored telephone number when the callback time arrives. If the call does not get through, the arrangement repeatedly periodically repeats placing of the outgoing call, until the call gets through or the callback time-period expires. When it places the outgoing call, the arrangement connects the originating end thereof to an ACD agent to handle the call.

Abstract: A CDMA cellular radio-telephone system (FIG. 2) has switching systems (201) synchronized to public telephone network (100) timing signals (600), and radio telephones (203) and cell base stations (202) synchronized to different clock (1000). Transmission delays between the cell base stations and the telephone network are variable. Switching systems include digital communications interfaces (264) to the telephone system, whose connections to the telephone system are synchronized to the telephone system, and whose connections to the cells are nominally also synchronized to the telephone system but whose processor (602) operates for each call within predefined windows (1302, 1402) of phase relationships to the operation of the cell that is handling the call, and occasionally adjusts (FIGS. 13-16) its phase relationships to the operation of the telephone system to achieve and maintain its operation within the predefined windows.

Abstract: To ensure delivery of inter-process messages at the same priority level at which they were sent in a multiprocessor (20), each message (200) includes a field (201) that indicates the priority of the sending process. When a message is received on a processor, a message-delivery function (22) determines whether the priority indicated by the message's field is lower than the priority of a process presently running on the processor. If not, the message is immediately delivered to the destination process; if so, the message is stored in the one queue of a plurality of queues (301-303) on the processor that corresponds to priority indicated by the message's field. Upon change of running process on the processor, the message-delivery function causes delivery to destination processes of messages stored in queues of the processor that correspond to priorities at least as high as the priority of the about-to-be-run process.

Abstract: In a multiprocessor system (FIG. 1), the processors (10-12) are interconnected by a non-blocking communication medium such as a crossbar switch (19). Each processor is connected to a dedicated port circuit (18) at the switch by an optical link (16). Each port circuit is connected to the crossbar switch by an electrical link (20). The port circuits are interconnected by a contention medium (14). A port circuit sends an access request by its connected processor to the destination processor over the contention medium. Circuitry (205) at each port circuit receives requests, for access to the connected processor, prioritizes conflicting requests, and grants them sequentially. The circuitry interleaves grants of access to the connected processor with grants of outgoing access requests made by the connected processor. The circuitry grants an access request by causing the crossbar switch to establish the corresponding connection.

Abstract: In a master-slave multiprocessor (FIG. 1), a slave processor (110) includes a random access memory array (119) that serves at initialization time as the slave processor's boot memory and that serves during normal operation time as the slave processor's cache memory. A master processor (120) writes the slave processor's boot program into the memory array when the memory array is to serve as the boot memory, i.e., following system reset.

Abstract: In a distributed system, such as a PBX (FIG. 1), which uses a database for its operation, a master copy (22) of the database having a first format is stored at a central node (10) and cache copies (32) of database portions (24) but having a different format are stored at peripheral nodes (11-12). A change to the database is made to the master copy, is recorded in a change table (26) corresponding to the affected database portion, and is sent to affected peripheral nodes. At initialization, a boot copy (25) is made of each database portion by translating the database portion from the master database format to the cache copy format. Periodically thereafter, each boot copy is replaced with a new boot copy that reflects changes presently recorded in the corresponding change table. When the new boot copy is generated, the present change table contents are erased. When a peripheral node calls for a new cache copy (e.g.

Abstract: A link interface to a high-speed asynchronous multiplexed ATM telecommunication link includes a data segmenter for forming ATM cells out of data frames, and a data assembler and state memory for assembling data frames out of received multiplexed (interleaved)ATM cells. A novel architecture implemented in hardware, and characterized by absence of intermediate storage of data in the data segmenter and pipelined operation of the data assembler, allows the link interface to operate at hundreds of Megabits and Gigabits per second.

Abstract: A non-blocking broadband broadcast time-division switching system (10) comprises a time-slot replication stage (12) followed by a conventional TMS stage (11). The replication stage replaces the TSI stage of conventional switching systems. Time division multiplexed links (16) are connected to inputs of the system. Each input link is connected to the input of a different replicator (14). Each replicator has as many outputs as there are time slots (202) in a frame (201) on an input link. Replicators' outputs are connected each to a different input of the TMS stage. In one embodiment, a replicator generates each time slot of a received frame at a different output and replicates the individual time slot at the individual output during each time-slot interval of a frame interval. In another embodiment, a replicator generates each time slot of a received frame at a different time at each output, thus generating a delayed replica of the received frame at the outputs.

Abstract: Telecommunication terminal administration is facilitated by a graphical user interface which uses an on-screen graphical display of a representation of a terminal including its actuators and a display of a list of telecommunications functions assignable to the actuators, a pointing device such as a mouse to select representations of actuators and functions, and a single assigning, or mapping, operating function "copy from-modify-replace to" to assign selected functions to selected actuators of the terminal whose representation is displayed and to assign terminals to locations, (e.g., extension lines and numbers), as well as to modify values of function attributes. The assignments are preserved for future use in the telecommunications system, so that when an actuator to which a function was assigned is actuated on the terminal whose graphical representation was displayed and which is located at its assigned location, the assigned telecommunications function is performed.

Abstract: A computer network (FIG. 1) comprises a plurality of personal computers (PCs 10), groups of which are each logically connected to a different one of a plurality of intermediate computers (11). At least one of the intermediate computers is connected to a mainframe computer (12). File and resource serving and locking services are provided transparently to PC user programs (200). Certain user service requests ("open file" and "exit" calls) on each PC to the PC operating systems means (20,22) are trapped by an operating system kernel-level patch (21), and corresponding requests are sent to a kernel-level driver (31) on the associated intermediate computer. The driver collects requests from all PCs associated with the intermediate computer and funnels them to a user level request server (32) on the intermediate computer.

Abstract: A master-slave multiprocessor (FIG. 1) is formed by connecting a slave processor (25) to an I/O slot of a uniprocessor, and by minimally modifying the uniprocessor's operating system. At initialization, one routine (FIG. 5) redirects slave interrupt vectors (200) to point to a common interrupt handler (FIG. 12). Before a process executes on the slave processor, another routine (FIGS. 9 and 10) corrupts execution stack bounds (217, 218) of the process. A non-interrupt operating system call during execution of the process causes an automatic firmware check (FIG. 3) of the execution stack pointer (203) against the stack bounds. Occurrence of an interrupt or encounter of a stack exception results in suspension of process execution and invocation of the interrupt handler or a slave stack exception handler (FIG. 11), respectively. Each handler calls a slave delete routine (FIG. 15) to restore the process' stack bounds to valid values and to transfer the process for execution to the master processor (12).

Abstract: In an optical differential signal transmission system, both the optical signal and its complement are transmitted via a single optical fiber, by using wavelength-division multiplexing. In a multipoint transmission system, tri-stateable differential optical signal transmitters and receivers capable of discerning tri-state differential optical signals are used, to allow a plurality of signal sources to share the same optical signal transmission path on a time-division multiplexed basis.

Abstract: A distributed control arrangement for a multi-mode circuit-switching or circuit- and packet-switching system avoids disadvantages attendant to a centralized control center and offers flexibility in the sourcing of communication-routing information. The switching system communicatively interconnects a plurality of communication endpoints, such as PBXs, and includes a plurality of circuit-switching units interconnected with each other and with the endpoints by at least one communication medium. Control is effected through a plurality of logical links of the LAPD communication protocol, one of which extends through the medium between each pair of adjacent units and of adjacent unit and endpoint. Each unit is responsive to receipt of a messeage that specifies a route of a circuit-switched communication path through the system, including through the receiving unit.

Abstract: In a multiprocessor system (FIG. 1) wherein each adjunct processor has its own, non-shared, memory (22) the non-shared memory of each adjunct processor (11-12) comprises global memory (42) and local memory (41). All global memory of all adjunct processors is managed by a single process manager (30) of a system-wide host processor (10). Each processor's local memory is managed by its operating system kernel (31). Local memory comprises uncommitted memory (45) not allocated to any process and committed memory (46) allocated to processes. The process manager assigns processes to processors and satisfies their initial memory requirements through global memory allocations. Each kernel satisfies processes' dynamic memory allocation requests from uncommitted memory, and deallocates to uncommitted memory both memory that is dynamically requested to be deallocated and memory of terminating processes.