Abstract: A system, method, and computer program product for performing edits on related curves by automatically defining an associative entity that is upstream of either curve being connected. The connecting entity is called an ‘intermediary’. When creating a connection between curves, irrespective of where they appear in the associative tree, their geometry is made dependent on a common intermediary that is placed upstream of both curves in the tree. With this structure, both curves are related to the intermediary but retain all the properties of being connected to each other. Any edit performed to either curve is redirected through the intermediary such that both curves are simultaneously modified, providing the user with bi-directional propagation of edits. The user does not need to keep track of the order that the curves were related.

Abstract: An operational amplifier having a low impedance input and a high current gain output. The operational amplifier comprises: 1) a first N-channel transistor having a source coupled to the low impedance input of the operational amplifier; 2) a first constant current source coupled between the source of the first N-channel transistor and ground; 3) a first amplifier stage having an input coupled to the first N-channel transistor source and an inverting output coupled to a gate of the first N-channel transistor; 4) a second amplifier stage having an input coupled to a drain of the first N-channel transistor and an output coupled to the high current gain output of the operational amplifier; and 5) an internal compensation capacitor coupled between the input and the output of the second amplifier stage.

Abstract: A differential difference amplifier is provided for amplifying an input signal having a magnitude close to zero (or a negative supply voltage) and adding an offset voltage to the amplified input signal.

Abstract: There is disclosed high-speed current-mirror circuitry and methods of operating the same. An exemplary impedance-peaking current mirror comprises a N-channel drive transistor and a N-channel mirror transistor. The N-channel drive transistor has a source coupled to ground, a drain coupled to a current source and a gate coupled to the drain via a series connection of a resistor and an inductor. The N-channel mirror transistor has a source coupled to ground, a gate coupled to the drain of the N-channel drive transistor, and a drain coupled to a positive power supply via an impedance load.

Abstract: A dynamically configurable replacement technique in a unified or shared cache reduces domination by a particular functional unit or an application such as unified instruction/data caching by limiting the eviction ability to selected cache regions based on over utilization of the cache by a particular functional unit or application. A specific application includes a highly integrated multimedia processor employing a tightly coupled shared cache between central processing and graphics units wherein the eviction ability of the graphics unit is limited to selected cache regions when the graphics unit over utilizes the cache. Dynamic configurability can take the form of a programmable register that enables either one of a plurality of replacement modes based on captured statistics such as measurement of cache misses by a particular functional unit or application.

Abstract: A resistor tuning network for an RC filter has a first, fixed resistor and a second, variable resistance connected in parallel with the fixed resistor. The variable resistance is an R-2R ladder circuit having an input and first and second output terminals, with a first line having a plurality of first arms connected in series with the input and first output terminal and nodes between each pair of arms, each arm having an identical resistor R. A series of shunt arms are selectively connected between the respective nodes and the first or second output terminal. Each shunt arm has a 2R resistor and a switch in series, and each switch has a first, closed position connecting the shunt arm to the first output terminal and a second, open position connecting the shunt arm to the second output terminal, such that the resistance of the ladder network is varied dependent on the switch positions and is at a maximum value when all switches are closed and a minimum value when all switches are open.

Abstract: There is disclosed a comparator comprising: 1) a first comparison circuit capable of receiving an input signal, wherein the first comparison circuit is enabled and compares the signal when a received LATCH signal is enabled and is disabled when the received LATCH signal is disabled; and 2) a second comparison circuit coupled to the input signal in parallel with the first comparison circuit, wherein an input stage of the second comparison circuit is substantially identical to an input stage of the first comparison circuit. The second comparison circuit is enabled and compares the input signal when the received LATCH is signal is disabled and is disabled when the received LATCH signal is enabled.

Abstract: An apparatus and method is disclosed for providing a phase locked loop clock divider circuit utilizing a high speed linear feedback shift register with a two stage pipeline in its feedback path. A plurality of “pre-load” flip flop (PLFF) circuits and multiplexers are coupled to a plurality of linear feedback shift register (LFSR) flip flop circuits and multiplexers. The PLFF circuits hold pre-calculated initial LFSR sequence values to be loaded into the LFSR flip flop circuits. The load enable signal to the PLFF multiplexers and to the LFSR multiplexers is low for three successive input clock cycles. The present invention is capable of operating at high frequencies due to a shortened timing critical feedback path.

Abstract: For use in an integrated circuit interface to a memory device, there is disclosed an input circuit having an input interface that is capable of receiving one of a high speed, high power signal and a low speed, low power signal. The input circuit of the present invention is capable of preventing direct current leakage within the input circuit when the input circuit is operating in a low speed, low power mode. The input circuit of the present invention comprises a multiplexer that is capable of receiving both high speed, high power signals and low speed, low power signals. The input circuit of the present invention also comprises a switch that is capable of preventing a high speed, high power signal from causing direct current leakage within the input circuit when the input circuit is operating in a low speed, low power mode.

Abstract: An apparatus is disclosed for implementing a complex filter of the type represented by a transfer function having a complex pole. The apparatus is capable of creating real and imaginary parts, Yr and Yi, of a complex output signal in response to receiving real and imaginary parts, Xr and Xi, of a complex input signal. The apparatus comprises a plurality of variable resistors that may be tuned to adjust various operating parameters of the complex filter.

Abstract: There is disclosed an adaptive voltage power supply that finely adjusts VDD to an optimum level. The adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; 2) a second charging circuit capable of decreasing the reference voltage on the charge capacitor in response to receipt of a second VDD control signal; and 3) a power supply capable of receiving the reference voltage on the charge capacitor and generating an output power level, VDD, determined by a level of the reference voltage.

Abstract: A low power analog equalizer is disclosed that provides up to twenty decibels (20 dB) of alternating current gain in a single stage of analog signal equalization. The analog equalizer comprises an operational amplifier coupled to two half circuits. Each half circuit comprises an impedance network capable of receiving an analog input voltage and generating a current signal that is inversely proportional to frequency, a current steering digital to analog converter capable of adjusting the gain of the operational amplifier, and a transistor and an amplifier coupled in a cascode configuration to create a low impedance node at the output of the impedance network. The analog equalizer is fabricated with 0.18 micron CMOS technology and operates at 1.8 volts.

Abstract: A voltage regulator formed on an integrated circuit is provided that includes an amplifier and a feedback circuit. The amplifier is operable to receive a reference voltage and a feedback voltage. The amplifier is also operable to generate a regulated output voltage based on the reference voltage and the feedback voltage. The feedback circuit, which is coupled to the amplifier, is operable to generate the feedback voltage. The feedback circuit includes an inductor-capacitor network. The inductor-capacitor network is operable to remove high frequencies from the output voltage.

Abstract: A band-gap reference circuit with offset cancellation is provided that includes a differential amplifier circuit. The differential amplifier circuit includes a first input node and a second input node. The first input node is operable to receive a first input signal. The second input node is operable to receive a second input signal. The band-gap reference circuit is operable to alternate between a first state and a second state based on a specified duty cycle. The first input node is an inverting node and the second input node is a non-inverting node in the first state, and the first input node is a non-inverting node and the second input node is an inverting node in the second state. The differential amplifier circuit is operable to generate an output signal based on a difference between the first and second input signals.

Abstract: There is disclosed, for use in an x86-compatible processor, an interface circuit for synchronizing the transfer of signals between different clock domains derived from a common core clock, where the phase and frequency relationships between the different domain clocks are known.