Abstract: A level shifter circuit suitable for high voltage applications with shoot-through current isolation is presented. The level shifter receives a first enable signal and receives an input voltage at a first node and supplies an output voltage at a second node. The circuit provides the output voltage from the input voltage in response to the first enable signal being asserted and sets the output node to a low voltage value when the first enable signal is de-asserted. The level shifting circuit includes a depletion type NMOS transistor, having a gate connected to the output node, and a PMOS transistor, having a gate connected to the first enable signal. It also includes a first resistive element that is distinct from the NMOS and PMOS transistors. The NMOS transistor, the PMOS transistor and the first resistive elements are connected in series between the first and second nodes, with the NMOS transistor being connected to the first node.

Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.