Patents Represented by Attorney, Agent or Law Firm Deborah Wenour
  • Patent number: 6472308
    Abstract: An improved manufacturing process and an improved device made by the process for forming via interconnects between metal layers in a multilevel metallization structure substantially eliminates trench formation during via overetch and exploding vias during via fill. An insulating multilayer structure comprising a conformal oxide, a spin-on layer, and an etch stop layer for the via etch locally planarizes the region adjacent to metal lines before the ILD is deposited and vias are patterned and etched. Using this process, metal borders around vias can be reduced or eliminated, thereby increasing circuit packing density.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: October 29, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Sunil D. Mehta
  • Patent number: D596859
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: July 28, 2009
    Inventors: Jeffrey Castaline, Hiroyuki Kobayashi