Abstract: A system (22) for synthesis of textured images, comprising a texture analyser (24) and a texture synthesizer (28). The texture analyser (24) comprises an analyzing neural network (30) which learns to characterize a texture by calculating synaptic coefficients (C.sub.ab), utilizing at least one proximity function which characterizes a neighbourhood around pixels of said texture. The texture synthesizer (28) comprises a synthesizing neural network (40) which receives the synaptic coefficients (C.sub.ab) thus calculated and which, utilizing a relaxation mechanism, synthesizes a replica of the texture learned. The neural networks (30), (40) may have a tree-type structure.

Abstract: A multi-media system for interactive presentation of user information has a physical interface for receiving removable and unitary mass storage elements for therein storing an interactive user program, and selectively accessing the mass storage element. The system accesses and processes the user program, for subsequent display of processing results, in response to particular user actuation on a level of elementary user functionality. In particular, the processing includes blockwise conversion to object code of machine-type generic multi-instruction blocks read from the storage to machine-type specific object-code blocks for subsequent selective accessing of the object code for processing.

Abstract: A microcontroller routs bits of a PSW to and from a bus depending on a mode. Whenever in a mode compatible with a prior generation microcontroller, address and routing circuitry using decoders and multiplexers, during a read operation, places bits of the PSW of the current generation on the bus at a location of the prior generation microcontroller. In a write operator circuitry also moves bits from the bus in an arrangement compatible with the prior generation and stores them in the arrangement of the current generation. The circuitry also allows various units such as the ALU to update the PSW register bits directly without making a bus transfer.

Abstract: A computer system includes a single-chip central processor (20) with handshaking and direct memory access (DMA) controllers for accommodating first and second types of DMA to a dynamic random access memory (DRAM) (34). The single-chip central processor (20) has a kernel processor (22) having cache, a memory management and control unit (26), and a coprocessor (24). The computer system further includes a bundle of lines (28), including data lines, address lines and row address strobe (RAS), column address strobe (CAS), output enable (OE), and write enable (WE) lines for coupling the memory management and control unit (26) to the DRAM (34), and a plurality of data exchanges (33, 37) coupled to a plurality of first and second attach controllers (32, 36). The coprocessor includes a plurality of DMA controllers (240-246) for storing addresses and for storing a length representing a number of data items to be transferred.

Abstract: In processors, notably digital signal processors, it is often necessary to form the sum of products of a concatenation of data word pairs, for example for correlation or convolution operations, in which the one data word of each pair can assume only one of the two values +1 or -1. In accordance with the invention, in that case instead of forming a product in a multiplier, the one data word of each pair is applied to an add/subtract device in order to control the function thereof in respect of addition or subtraction; one input of the add/subtract unit then receives the other data words of the data word pairs, and the other input is connected to the output of the accumulator register. Thus, a complex multiplier device is saved or, should such a device be present anyway, it will not be used so that the power loss of the processor is reduced.

Abstract: On the basis of a device without hidden neurons, arbitrary samples are taken from a set of learning samples so as to be presented as objects to be classified. Each time if the response is not correct, a hidden neuron (H.sub.i) is introduced with a connection to the output neuron (O.sub.j) of the class of the sample, whereas if the response is correct, no neuron whatsoever is added. During this introduction phase for hidden neurons, the neurons are subdivided into groups by searching for each of the introduced neurons whether it falls within an existing group, in which case it is incorporated therein; otherwise a new group is created around this neuron. The association with a group is defined as a function of the distance from the "creator" neuron. This device could be applied in character recognition systems as one example.

Abstract: The neural net has a physical topology independent of its functional topology. Cells, being functional equivalents of synapses, are concatenated to form a unidirectional data path. The cells are connected in parallel to a bus for individual or parallel control The respective synapses contributions to a neuron potential are individually calculated in each respective cell involved. Each cell in the concatenation either is rendered transparent or adds its contribution to the data received from the preceding cell and supplies this sum to the next cell. Preferably, the allocation of the synapses to the cells is programmable.

Abstract: This device is designed for carrying out a division of a dividend A formed by "m" words with a base "b" by a divisor D. It comprises an active memory (2), a multiplication member which forms part of a calculation unit (8) provided with a first input (x.sub.i) for "x" words of a multiplicand and with a second input (A.sub.i) for "y" words of a multiplier. Accumulating means are provided for adding to locations of the memory (2) a multiple of a quantity db.sub.k.multidot. b.sup.j worked out by the said multiplication member, as well as testing means for providing an indication of the zero value of a separator S in the said location, and for activating the cumulation means until the testing means provide the said indication, as well as decrementation means for decrementing the value J at each indication. The remainder of the division is present in the last locations, and the quotient in the first ones.

Abstract: A cell in a multiport memory is connected to a respective bit line via respective switches. A write enable element is located between the switches and an input of the cell's storage device. A read enable element is located between an output of the storage device and the same switches. Thus, read bit lines and write bit lines are merged and the number of switches per cell is drastically reduced with respect to prior art multiport memories.

Abstract: The procedure for the recognition of a speech signal until output of the recognized word sequence or the recognized sentence is split in accordance with the invention in such a manner that first only word hypotheses are separately generated for different starting instants and that from these word hypotheses preliminary word strings are formed in conformity with a word graph, the word graph thus arising being continuously optimized by erasure of parts of word strings. Parts of word strings having the same beginning and end points are compared with one another and the scores of words having concurrent end points are compared with a threshold value. Further steps for optimization of the word graph are also shown. For output disclosed a particularly effective post-editing operation where for each incorrect word all further words having the same beginning are output, enabling fast selection of the correct word from all said further words, by the operator.

Abstract: A neural processor, including neural calculation apparatus (30, NQ, RQ) which normalize an input data X with respect to another input data Y. The calculation apparatus performs a division of X by Y in order to determine a quotient Q. The calculation apparatus is trained to calculate by iteration a series of contributions .DELTA.Q.sub.i which are used to update a partial quotient QP which becomes the quotient Q at the end of calculation. Calculation can be performed on an arbitrary arithmetic base which determines the number of neurons utilized and also the accuracy of the calculation. It is also possible to utilize a partial remainder RP.

Abstract: A data communication system comprises a main device with a first microcomputer and an operating device with a second microcomputer. The devices are connected to each other by a first wire and by a second wire. In addition to that, input interrupt terminals of both devices are connected to the second wire. One device starts the sending of data by pulling the second wire to a first level, the detection of this by the other device is signalled back via the first wire and both devices then start an internal timer. When a predetermined time, corresponding to a data item to be sent, has lapsed the sending device pulls the second line again to the first level. This is detected by the other device, which measures the lapsed time and which uses this time to determine the data item sent by consulting preset conversion rules, that give a relation between time and a data element.

Abstract: An instruction prefetch system for a digital processor, and in particular a microcontroller which includes the prefetch system and instruction queue normally provided as part of the instruction fetch unit, to which is added a second instruction prefetch buffer in the system, preferably in the bus interface unit which serves as the memory interface unit. This added prefetch buffer has storage for only a small number of bytes or words, and operates to supply prefetched instructions to the queue in the instruction fetch unit. However, it operates under the following constraint: it only prefetches within the boundaries of each small block of code memory and stalls when a block boundary is reached until a new address appears. This approach combines some cache and prefetch principles for a limited cost design.

Abstract: In the recognition of coherent speech, language models are favourably used to increase the reliability of recognition, which models, for example, take into account the probabilities of word combinations, especially of word pairs. For this purpose, a language model value corresponding to this probability is added at boundaries between words. In several recognition methods, for example, when the vocabulary is built up from phonemes in the shape of a tree, it is not known at the start of the continuation of a hypothesis after a word end which word will actually follow, so that a language model value cannot be taken into account until at the end of the next word. Measures are given for achieving this in such a manner that as far as possible the optimal preceding word or the optimal preceding word sequence is taken into account for the language model value without the necessity of constructing a copy of the searching tree for each and every simultaneously ending preceding word sequence.

Abstract: The neural net has a physical topology independent of its functional topology. Cells, being functional equivalents of synapses, are concatenated to form a unidirectional data path. The cells are connected in parallel to a bus for individual or parallel control The respective synapses contributions to a neuron potential are individually calculated in each respective cell involved. Each cell in the concatenation either is rendered transparent or adds its contribution to the data received from the preceding cell and supplies this sum to the next cell. Preferably, the allocation of the synapses to the cells is programmable.

Abstract: A table contains codes for consecutive decimally numbered pages and pages whose numbers contain hexadecimal digits. Codes for all the pages having decimal units numbers are arranged in rows and columns such that a column contains codes for pages having a same units number, and codes for pages having a same tens number (whether decimal or hexadecimal) are in the same row. Codes for pages having a hexadecimal units number are arranged in a continuation of the rows and columns, hexadecimal units being arranged in the columns under the corresponding decimal units.

Abstract: Transmitter station for transmitting a plurality of television programs, and receiver for receiving the programs.Transmitter station for transmitting, and receiver for receiving a plurality of television programs via respective transmission channels. A teletext page with tuning data which are representative of the transmission channels used by the transmitter station is transmitted by means of one of the programs, for example a local television program. An installation procedure of downloading the tuning data comprises the search of the local television program. In order to accelerate the procedure, the page header of its teletext pages includes a code (.about.) indicating that the tuning data are incorporated in said television program.

Abstract: A video camera is displaced to successive positions a displacement distance that differs from each preceding position by a factor of two wherein the camera image plane is at a constant distance from an object whose distance from the camera is to be estimated. The further that the camera is moved the more accurate the estimated distance. The camera is displaced a relatively small increment initially to provide an accurate estimate of the corresponding pixel of interest in the next camera position. The successive displacements increase rapidly to relatively large values, to which the estimated pixel disparity corresponds to give a relatively accurate camera to object distance estimate. The window size and position of each successive camera position for each pixel of the image can be accurately estimated to reduce potential error in pixel disparity estimation.

Abstract: Method and device having a neural network for classifying data, and verification device for signatures.The device includes a neural network with an input layer 3, an internal layer 4, and an output layer 5. This network is designed to classify data vectors to classes, the synaptic weights in the network being determined through programming on the basis of specimens whose classes are known. Each class is defined during programming as corresponding to a set of neurons of which each represents a domain which contains a fixed number of specimens. The network includes a number of neurons and synaptic weights which have been determined as a function of the classes thus defined.

Abstract: An arrangement for recording data, such as for example, teletext data, on standard domestic video recorders includes a teletext decoder and a microprocessor. The teletext decoder acquires selected teletext pages and passes them from its memory to the microprocessor over a bus as original standard teletex data packets. The microprocessor converts a teletext data packet into a plurality of data blocks, each of which is expanded to occupy a majority of an active line period. Thus the instantaneous data rate is reduced. The expanded data blocks are passed to video recorder circuitry via a shift register and switch. On replay, the microprocessor generates synthetic page and row headers to enable the teletext decoder to acquire data blocks from recording medium in the video recorder, as though the data blocks were standard teletext packets.