Abstract: A multiport register file includes a first file unit having registers of a first width and a second file unite having registers of a second width. The second width being less than the first width. The first file unit accommodates data destined to be operands for functional units of a VLIW processor, or result data from those functional units. The second file unit accommodates guard bits for conditioning operation of those functional units.

Abstract: A data bus system has a number of stations which are interconnected via a bus. The bus has a limited data transmission capacity available. From a transmitter station a resource control station reads which part of the available transmission capacity is required for the relevant transmitter. The resource control station allocates the required transmission capacity to the relevant transmitter station if adequate transmission capacity is available. Only if adequate transmission capacity is available is transmission by the relevant transmitter station enabled.

Abstract: The test apparatus (PC,KB,DIS,PR,IF) communicates via a standard serial bus (12) with a device under test (DUT) to verify conformity with a standard application protocol defining the format, meaning and applicability of messages passed via the bus (12). The apparatus generates a test sequence of commands and requests and analyses the replies of the DUT for conformity. The test sequence and the analysis are adapted automatically in response to previous replies of the device, to provide a thorough but efficient test of the device and any subdevices identified within it. Where the standard application protocol defines extended autonomous cooperation between devices, the test apparatus emulates one or more further devices to be controlled and interrogated by the device under test.

Abstract: The communication system allows a group of at least three apparatuses, such as game computers and Personal Digital Assistants (PDAs), to communicate wirelessly by using, for instance, infrared transmission. The apparatuses are the same from a communication point of view. A message frame (500) transmitted by an apparatus (10) can, therefore, be received by all other apparatuses (101 e.a.), which are part of the system. Reliability is increased by acknowledging correct reception of a message frame (500) and retransmitting a message frame (500) up to a predefined maximum number of times if no acknowledgement frame (510) is received. The chance of message frames (500) and/or acknowledgement frames (510) colliding is reduced. After a message frame (500) has been transmitted, a following defined time period is reserved for acknowledging reception of the message frame (500). Upon receiving the message frame (500), the receiving apparatuses (101 e.a.

Abstract: A microcontroller or processor architecture that performs word aligned multi-byte fetches but allows byte aligned instructions. Jump target addresses are word aligned, resulting in a word aligned fetch of the jump-to instruction. An assembler or compiler loads code into an instruction memory with branch instruction target addresses aligned on word boundaries. Returns from interrupts load the program counter with a complete return address which is byte aligned.