Abstract: Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided.
Type:
Grant
Filed:
July 15, 2008
Date of Patent:
March 1, 2011
Assignee:
International Business Machines Corporation
Inventors:
Kenneth Pichamuthu, Prakash Venkitaraman, Andrew Ferko
Abstract: A method of installing a satellite dish mast, comprises providing a mast member including a generally cylindrical wall and having an aperture therethrough, and providing a level mounted interior of the mast member but visible from outside the mast member through the aperture in the mast member; and adjusting the position of the mast member using the level and securing the position of the mast member.
Abstract: A satellite dish assembly comprising a mast member having an open end and a level mounted interior of the mast member and visible through the open end of the mast member.
Abstract: A system comprising a server having a memory, and a database defined in the memory; and a client in communication with the server, the server communicating to the client an interface for use in requesting a search of the database, and the server having virtual reality means for generating a virtual reality scene, the virtual reality scene varying depending on the results of the search.