Abstract: A digital filter is described which is based on the use of the so-called primitive roots transform and its inverse. This transform converts a series of binary numbers {a.sub.n } into a transformed series ##EQU1## WHERE G IS A PRIMITIVE ROOT OF A PRIME NUMBER P, AND THE VALUES BETWEEN SUPERFLUOUS PARENTHESES ARE TAKEN MODULO P. Said filter is provided with input means for applying fixed length data blocks made of a group of input samples appended with an equal number of zeros to the input of at least one circular convolutor. This convolutor is provided with accumulating means for generating multiples of each a.sub.n term, adding means for generating said A.sub.k terms by adding successively provided multiples of a.sub.n to selected partial terms of A.sub.k, and means for storing said partial A.sub.k terms as they are formed. There is also a device for storing the Primitive Roots transform B.sub.

Abstract: The invention covers a precision digital filter for signal samples represented in a digital form. The flow of samples x.sub.o, x.sub.1, x.sub.2, . . . x.sub.n, of the signal is split into blocks of a fixed length which are simultaneously transmitted to two circular convolution generators operating to different prime number modulos. The outputs of the generators are each submitted to a correcting device and the corresponding corrected terms are added. The added terms are each then added to a delayed prior term to generate representations of samples of a filtered signal.

Abstract: In the application of analog type circuits to semiconductor chips for large scale circuit integration, a substantial improvement in the size of an amplifier circuit on the chip can be obtained by use of only active components on the chip. The described circuit is designed for any desired amplification factor and this factor can be maintained substantially uniform from chip to chip despite wide variations in the characteristics of comparable components between different semiconductive chips. The analog amplifier includes a high gain operating amplifier and a feedback-input circuit having only active components and which can be designed to reduce the gain of the operating amplifier to any desired value.

Abstract: This is a block quantizer which converts a given block of samples into an optimum sequence of numbers describing the sampled signal with minimum distortion due to the quantizing process.The quantizer self-adjusts the basic parameters, i.e., quantizing step Q, d.c. level C and the sequence of numbers fn, describing the signal for each block of samples for a minimal Mean Squared Error.

Abstract: A digital filter is disclosed which includes a circular convolution device using the Complex Mersenne transform to convert a sequence of values A.sub.n into another sequence A.sub.k in which ##EQU1## WHERE P IS PRIME NUMBER AND J IS THE SQUARE ROOT OF MINUS ONE. The convolutor is provided with an input for applying fixed length data blocks made up of input samples appended with an equal number of zeros; circuits for recirculating and accumulating said data; a register for storing said accumulated data; switches for selectively connecting the output of the storage to the inputs of an adder-subtractor; a product device for term-by-term multiplying of the output of the adder-subtractor with the Complex Mersenne transforms of the filter coefficients set appended with zeros; and an inverse transform device for performing the inverse Complex Mersenne transform on the multiplier output blocks of data.

Abstract: A statistical data detection method for use in a synchronous data transmission system employing either phase modulation, combined amplitude and phase modulation or quadrature amplitude modulation. The signal space diagram of the possible states of the transmitted signal and their influence zones is divided into N elementary squares. Since the squares are rather coarse to save storage space, many such squares belong to more than one influence zone. The influence zone of a state Z defines the region within which the received signal, P, will lie when state Z has been transmitted.A word in a ROM is assigned to each elementary square, and each word comprises two entries. The entries are identical when a square falls wholly within a single influence zone. Otherwise, the entries are different. Parts of the received signal are converted into an address for addressing the ROM.

Abstract: A clock setting circuit is provided at a receiving modem for adjusting the phase of a timing signal defining the signal sampling instants. The received signal is filtered in two filters to derive a first signal having a phase .phi..sub.1 and a frequency f.sub.1 equal to f.sub.c - 1/2T, f.sub.c being the carrier frequency and 1/T being the transmission baud rate, and a second signal having a phase .phi..sub.2 and a frequency f.sub.2 equal to f.sub.c + 1/2T. The first and second derived signals are combined to derive an error signal indicative of the phase difference .phi..sub.2 - .phi..sub.1 which difference is used for adjusting the phase of a phase locked oscillator which provides the timing signal.

Abstract: A data processing machine specifically designed to use a single format of instructions for all operations. The format provides for sufficient information to be provided to enable complex functions to be performed in response to a single instruction. More particularly, a machine organization and an instruction format therefor are disclosed to enable one instruction to enter sufficient control data for control of a long repetitious operation. The instruction is in four sections to enable a function to be specified, to identify one or more operands to be utilized and to specify a number of times the function is to be performed or to specify another limit to the repetitions of the function.

Abstract: A decision feedback equalizer is described wherein an approximate value .alpha..sub.0 of the phase of the signal being received at sampling time t.sub.0 is obtained by subtracting a phase error (.theta..sub.0 - .alpha..sub.0) from the value .theta..sub.0 of the phase of the signal received at t.sub.0. Value .DELTA..sub.0 is fed to a decision logic which provides an estimated value .DELTA..sub.0 of the phase of the transmitted signal, which value is representative of the detected data. Value .alpha..sub.0 is fed to a decoder which provides its components in a Cartesian coordinates system. These components are fed to the inputs of a complex, cross-coupled equalizer which supplies the approximate values .DELTA.u.sub.0 and .DELTA.v.sub.O of the components, in a Cartesian coordinates system, of the distorting signal representative of all distortions introduced by the communication channel. The phase error (.theta..sub.0 - .alpha..sub.0) is obtained from the relationsin (.theta..sub.0 - .alpha..sub.0) = .DELTA.u.

Abstract: The disclosed circuit is to provide a current source for use on a semiconductor chip having field effect transistors (FET) deposited therein to compensate for variations in the substrate voltage source. Analog type circuits when alone on a semiconductor chip or combined with digital type logic circuits are normally susceptible to disturbances in the bias voltage applied to the substrate of the chip. The obtaining of a uniform output response from an analog type circuit due to an input voltage change has heretofore required the use of off-chip precision voltage sources. Such expensive precision sources can be eliminated and normally variable (.+-. 15%) supplies can be used by providing an on-chip compensating current source which combines with other circuits to provide stable reference voltage levels on the chip for use by the analog circuits.

Abstract: This invention features the use of two paralleled insulated gate depletion channel field effect transistors (FET) having their gates connected one to the source voltage and one to the drain voltage to provide a linear resistance element. The actual resistance value can be controlled by selecting design parameters and can be extended by using a plurality of such elements in series to provide greater resistances and/or higher voltage capabilities or in parallel to provide greater current capacity. The described resistor is used as a cost and space saving alternate to discrete resistor components and is particularly useful as a part of an integrated circuit in analog type devices.

Abstract: This invention discloses a structure whereby a fixed frequency machine clocking signal can be multiplied in frequency by any desired integral value. The device uses a tapped delay line having a total time delay slightly less than the time of one-half cycle of the clocking signal and an exclusive-OR tree connected to the taps of the delay line to generate a higher frequency output clock signal. By interposing a known frequency division network to the input of the delay line, the output clock signal can be generated with any desired rational relationship to the driving clocking signal.

Abstract: The subject of this invention is a differential amplifier circuit having a constant gain characteristic over a range of input voltage and suitable for use in integrated circuits in semi-conductor chips. The circuit is embodied in the enhanced-depleted field effect transistor technology and includes a pair of parallel circuits. Each circuit has a depletion type of field effect transistor (FET) connected to the drain voltage source, and its source connected to the drains of two enhanced FET's and to the gate of the one of these which has its source to a ground level. The other enhanced FET's have their sources connected together and to a constant current source. One gate of these other FET's is connected to the reference voltage and the other to an input voltage to be amplified. By a proper selection of FET design parameters, the amplifier gain can be constant over the full operating range of the input voltage.

Abstract: The structure described is a switching-processing node for high speed data transmission systems. Information is transmitted in time slot channels, one of which is control information. Data to be passed through a node is stripped of control characters, passed to a transmitting unit and there re-encoded with such additional data bits as needed. Data for the node is switched from an input decoder to a processor input and data for transmission is switched to a transmission unit for encoding.A switching information control frame can be passed over the system to set the switching circuits at a node to operate at the appropriate time slots of the data frames.

Abstract: A digital filter for a plural digitally expressed pulse code modulated (PCM) signal utilizes a storage register to retain several samples of the signal and obviates the need for digital multiplication circuits by using a delta coding for the filter coefficients. Processing steps are at a multiple of the sampling rate and at each step, the value of one stored sample is combined additively or subtractively with previously stored sample values as determined by stored delta coefficient values. The summed values are periodically transmitted as output samples of a filtered PCM signal.

Abstract: The feature of the invention is an adaptive equalizer for modulated carrier transmission systems in which a received signal is subjected to a Hilbert transformation to obtain a second signal having a 90.degree. phase shift for all components. The two signals are then passed through a pair of filters each and the outputs are cross-combined to generate the cartesian coordinate signals of an equalized signal. The coordinate signals are combined in a polar converter and are then decoded to detect the amplitude and phase data components of the received signal.The equalizers are made adaptive by determining at each sampling time, the phase and amplitude errors in the signal and using these errors to modify the coefficients of the equalizing filters. The phase and amplitude errors are recoded into Cartesian coordinates and multiplied by the values of the samples at each tap of the filters to generate four error signals for each tap.

Abstract: This disclosure is for an Audio-Visual training device having both a projectable film tape and an audio tape with control indicia on the audio tape in addition to recorded audio messages. The tape indicia are used to control a small processor which governs both tape and film movement. A keyboard on the device is used to enter replies to queries to a user from the tape and film and the processor will determine both tape and film movement in response to the answer to a query. The system is capable of multiway branching to present to the viewer the proper information pertaining to his answer. Several counters are available to count trials, correct or incorrect responses, etc., and to control tape and film movement in accordance with the counter readings. A proctor light may be turned on to call for personal assistance and to lock up the machine when a student is in trouble and the program does not have the proper branch to clear up the difficulty.