Abstract: A variable data barcode label, comprising sequence of barcodes integrated onto a substrate, the sequence of barcodes including a identification sequence and a reference sequence which defines the readable region of the barcode label; and a sensor integrated onto the substrate, wherein the output of the sensor measurement is located in the variable data field of the barcode label and is optically viewable by an optical reading device.

Abstract: The I/O bracket retainer is a unitary structure that provides excellent EMI shielding without the requirement of an additional gasket layer. EMI leakage is minimized by providing an I/O bracket retainer surface. typically stainless steel, that conforms to the surface of the I/O bracket retainer and I/O panel, thus minimizing seams formed due to small differences in the planarities of the I/O bracket retainer and I/O panel. EMI leakage is further reduced by providing firm contact between the surfaces of the I/O bracket retainer and I/O panel to minimize seam formation between these parts. Firm contact is provided in part by a first positioning tab and spring finger which extend from a sidewall of the structure to the front panel of the I/O bracket retainer. The front panel of the I/O bracket retainer is designed for receiving and securing an I/O panel. The I/O panel is positioned between the first spring member and positioning tab of the I/O bracket which helps provide firm contact to the I/O panel.

Abstract: The present invention provides an optimization tool that utilizes traffic data across collision domain boundaries to provide suggestions as to how the network should be changed to achieve an optimal network topology. The optimization tool identifies collision domains that are reaching their peak capacity and analyzes their traffic pattern data to determine whether these over utilized collision domain should be divided into smaller collision domains. Once traffic data is collected, the steps typically implemented by the optimization algorithm to determine the optimal network topology include: identifying and removing global talkers from the analysis; creating workgroups based on the network traffic patterns; for each workgroup, deleting any nodes that do not reside on the same collision domain as the rest of the nodes in that workgroup; analyzing the workgroups of each collision domain; inserting previously removed global talkers back into the analysis; and analyzing the global talkers.

Abstract: The present invention provides a vertical cavity surface emitting laser having high gain and high reflectivity in the desired wavelength range and good thermal and electrical conductivity. The laser structure is comprised of a first mirror region, a second mirror region, and an active region positioned between the first and second mirror regions. Unlike, prior VCSELs, the active region is fused to both the first mirror region and the second mirror region. This allows the laser designer to optimize laser performance for the desired wavelength range by allowing the choice of different materials for the first mirror region, the second mirror region, and the active region.

Abstract: A power distribution unit adapted for mounting within an equipment enclosure including an inner rack. The power distribution unit includes at least one mounting hinge that is fixedly attached to the power distribution unit housing and which is adapted to fixedly mount the power distribution unit to the rack columns. The mounting hinge is pivotable such that the power distribution unit can be pivoted to an extended position to facilitate removal of removable modules of the equipment components mounted within the equipment enclosure.

Abstract: The present invention is a mounting platform for placement of a first device on a first plane in close proximity to a second device on a second plane. In the preferred embodiment, the first device is a voltage regulator circuit, the second device is a microprocessor, the first plane is the surface of the platform printed circuit board (PCB), and the second plane is the surface of the base printed circuit board. Typically the microprocessor is electrically coupled to the base printed circuit board and the voltage regulator circuit is electrically coupled to the platform printed circuit board. The mounting platform is mounted as a mezzanine over the base printed circuit board on the platform printed circuit board. Mounting the voltage regulator in this way allows the voltage regulator output to be placed adjacent to the microprocessor chip while at the same time minimizing the amount of valuable board space that is used.

Abstract: The card removal method and system easily removes a PCA card from a powered on computer system while minimizing damage to the computer system and to the individual removing the PCA. The printed circuit assembly card removal system is comprised of: an ejection card including at least a first ejector extending from the surface of the ejection card, the ejector having a first surface for pressing against the edge of the PCA card to be removed, and an ejection card holder for mechanically supporting the ejection card. To remove the PCA, the ejection card is pulled outward causing the ejector to apply a force to the edge of the PCA card to be removed, forcing the card edge fingers of the PCA card out of the PCA connector.

Abstract: The present invention is a compiler optimization algorithm that reduces address computation overhead for architectures that support an auto-increment addressing mode for memory access instructions. The compiler algorithm identifies opportunities for auto-increment synthesis in a low level intermediate representation. Candidate loads and stores are transformed to use a base+displacement addressing mode (even if a base+displacement addressing mode is not supported in the target architecture) prior to instruction scheduling. After instruction scheduling, the pseudo (base+displacement) instructions are transformed back into memory operations that increment their base register operands to set up effective memory addresses.

Abstract: The present invention provides an efficient method for attaching computer system components which greatly reduces or eliminates damage to the PC board or components. The method for attaching the computer component includes the steps of: positioning the component on the PC board so that the component leads are aligned with the corresponding pads on the PC board; attaching the anchoring leads to its corresponding pads on the PC board; and heating the attachment media with a heated air jet so that the heated air jet heats the attachment media to a temperature between the melting point of the attachment media and the vaporization point of the attachment media, wherein the heated air jet is moved back and forth along the edge of the component being attached.

Abstract: The present invention provides a test and diagnosis system for testing an embedded processor. The test system includes an ASIC having an embedded microprocessor, a debug assist logic unit for monitoring the addresses and data from the embedded microprocessor, a debug kernel and an instruction overlay harness. When the debug assist logic block finds a predetermined set of match conditions, it interrupts the embedded microprocessor and transfers control from the code running on the microprocessor to the debug kernel. The debug kernel is coupled to the debug assist logic unit and responsive to user input, the debug kernel allows the user to trace processor transactions during code execution. A REMAP bit in the ASIC allows remapping of the microprocessor memory into a faster instruction overlay memory, allowing the code to be quickly modified during product debug.

Abstract: The present invention provides a method and apparatus for visually presenting the access frequency of a two dimensional image. The method includes the steps of: determining which defined regions of the image are accessed; determining the frequency that the plurality of defined regions is accessed; creating a graphical representation corresponding to the plurality of defined regions for the image, wherein the x axis of the graphical representation corresponds to the x axis of the image and the y axis of the graphical representation corresponds to the y axis of the image; and combining the graphical representation with an access frequency indicator to create an access frequency output that corresponds to the plurality of defined regions. From the access frequency output, the user can see the access patterns of the image and can easily visualize how frequently small portions of the image are accessed.

Abstract: The present invention provides a reliable high current connector for connecting the ground and power planes of a first PCB to the ground and power planes of a second PCB. The power bus bar is comprised of a first conductive structure having a first and second surface, a second conductive structure having a first and second, and an inner insulative structure positioned between the first surface of the first conductive structure and the first surface of the second conductive structure. A fastening means, inserted through openings in the conductive structures, provides a secure, low resistance electrical connection from the first or second conductive structure of the bus bar to the electrical traces of the PCB. The high dielectric constant of the insulator provides distributed capacitance between the first conductive structure and the second conductive structure, lowering the AC impedance.

Abstract: The present invention provides a voltage transformer circuit which combines half-bridge topology with a current-mode control according to the present invention. The DC--DC converter circuit according to the present invention includes: a power transformer, where the primary side of the transformer includes a power winding and a balance winding and a means for injecting a correction current proportional to the amount of current flowing in the balance winding, where the means for injecting a correction current proportionate to the amount of current flowing in the balance winding including a means for sensing the amount of current in the balance winding. The correction current is injected in such a way so that current from the means for injecting a correction current is subtracted from the switch current lengthening the on-time of the switches in the half-bridge circuit thereby driving the bridge center tap back towards V.sub.in /2, preventing an unstable or runaway operating condition.

Abstract: The present invention provides a lossless coding scheme that maps unconstrained binary sequences into sequences that obey the (d,k)-RLL constraint while offering a degree of DC control. In the preferred embodiment, the channel encoder is a state machine which uses a single "overlapping" table for all states rather than using multiple tables. Recognizing that a subset of codewords in a first state x.sub.i are identical to a subset of codewords in the second state x.sub.j, the overlapping encoding table uses identical addresses for the subset of identical codewords in the first and second state. Thus addresses for more than one state may point to a single codeword. A number of input bytes can be encoded into two different codewords which have different parity of ones, thus allowing for DC control. Decoding is carried out in a state-independent manner.

Abstract: The queue management control system according to the present invention provides a system that elegantly handles unlimited queue deletions without bubbles. The queue management control system is comprised of: a plurality of item registers; and a control logic block electrically coupled to the plurality of item registers. The control logic block includes an item tracking means, a plurality of pointer registers, and an item ordering means. The pointer registers are connected in a loop configuration so that the order of the contents of the pointer registers mirrors the behavior of a FIFO queue. Because of the one-to-one correspondence between the values stored in the pointer storage registers and the item registers, the contents of each pointer register may be mapped to a particular item register. This allows tracking of the order of the items in the item register to be serviced by the servicing logic by the contents of the pointer register.

Abstract: The present invention provides an inexpensive, automobile test diagnostic system which is capable of processing data from multiple high speed data channels. The vehicle test diagnostic system include an integrated computer for providing access to a technical database comprised of stored information records, with migration capacity between related records, and further to provide selective access to particular portions of information within the database, the integrated computer including a user interface responsive to operation by a user to provide commands, and a microprocessor responsive to commands entered through the user interface to access the information; and at least one instrumentation module electrically coupled to the integrated computer, the instrumentation module being responsive to commands entered through the user interface.

Abstract: The present invention provides an automotive test diagnostic system which is capable of achieving high data rates through multiple, independent instrumentation channels. The test diagnostic system includes a vehicle diagnostic instrumentation controller, the vehicle diagnostic instrumentation controller comprising: an instrument peripheral interface means; an instrumentation control means, the instrumentation control means being further comprised of an arbitration control means, and a device interface means, wherein the arbitration control means is electrically coupled to the device interface means; and a first bus for electrically coupling the instrument peripheral interface means to the instrumentation control means. In the preferred embodiment, the instrumentation control means further includes a data qualification means and a data storage means for storing data. However, dependent on the rate of data transfer, the calculations required, etc.

Abstract: The present invention provides an effective, low cost method and system for enhancing various types of images including photograph, CD, video, and graphic art images. The method of enhancing the input image, includes the steps of: filtering the input image to extract m different frequency components r.sub.k ; adaptively sharpening the m different frequency components r.sub.k, where the amount of sharpening for each component r.sub.k corresponds to a sharpening function g.sub.k ?r.sub.k !; and adding the adaptively sharpened m different frequency components g.sub.k ?r.sub.k ! to the input image. Because the sharpening function is typically nonlinear, the step of determining the value of the adaptive frequency component corresponding to the sharpening function is achieved by mapping the filtered component by the corresponding sharpening function.

Abstract: The present invention provides a structure and method for integrating a photodiode and surface emitting laser on a substrate which minimizes both process complexity and exposure of epitaxial layers. In a first embodiment, a photodiode structure is integrated with the surface emitting laser simply by adding a separate Schottky contact to the surface of the SEL. In a second embodiment, a photodiode structure is integrated with the surface emitting laser by positioning a current isolation region between the photodiode and the SEL. The current isolation region should extend into a first mirror region but not into the light generation region of the active region so that the light generation region of the SEL is optically coupled to the light absorption region of the photodiode.

Abstract: The present invention describes a system and method to efficiently implement case table constructs for integral datatypes larger than the native underlying register size of the architecture. The method for generating case table constructs for a n-bit case variable on a computer system having a m-bit architecture, where n is greater than m, includes the step of determining whether the n-bit case variable can be represented in m bits. Since the code for a m-bit case variable is more efficient than the code for a n-bit case variable, the present invention determines which case variables require code for n-bit values and which case variables can be implemented in the more efficient code for m-bit values. If the case variable can be reduced to m-bits then the present invention uses the more efficient m-bit case variable code for implementation. Otherwise, the less efficient n-bit case variable code is used. The invention describes an efficient method for performing this test at runtime.