Abstract: An encapsulation procedure for an organic light emitting diode (OLED) device, especially for thin and therefore flexible substrates, is disclosed. The device is sealed hermetically against environmental and mechanical damage. The procedure includes the use of a thin cover lid holder and a substrate holder that are designed to handle thin substrates without damaging them. Thin substrates ensure sufficient mechanical flexibility for the OLED devices, and provides an overall thickness of less than 0.5 mm.

Abstract: An OLED device having pillars with cross section that is wider on the top. The pillars structure a conductive layer during deposition into distinct portions located between the pillars and on the top of the pillars. In one embodiment, the grooves between the pillars extend outside the electrode region to prevent shorting of adjacent electrodes.

Abstract: A support for facilitating the bending test of flexible substrates is disclosed. The support includes a plastic or adhesive plastic applied on the substrate to keep the shards together after breakage, thereby eliminating the process of collecting the shards and fitting them back together for failure analysis.

Abstract: An OLED device using improved pillars to facilitate patterning of a conductive layer is described. Conventional use of pillars to pattern electrodes encounters shorting problems due to piling of polymer material at the base of the pillars. This piling deteriorates the profile of the pillars which adversely impacts the ability of the pillars to pattern the conductive layer to form the electrodes. The present invention avoids the shorting problem by separating the pillars into at least first and second sub-pillars. By providing a relatively narrow gap between the sub-pillars, the amount of polymers filling the area between the gap is small. This prevents at least the sidewalls of the pillars facing the gap from being deteriorated by polymer pile-up, thus ensuring that the conductive layer is discontinuous between the sub-pillars.

Abstract: A method of fabricating OLED devices is disclosed. A conductive layer is patterned by pillars to form electrodes in the device, wherein portions of the pillars have at least 2 sub-rows to prevent shorting of adjacent electrodes. In one embodiment, the ends of the pillars are split into at least 2 sub-rows.

Abstract: An improved method of fabricating a device such as OLED is disclosed. The method includes applying an adhesive on a cap or substrate. The adhesive is partially cured to initiate the cross-linking process while remaining in the liquid phase. The cap is then mounted onto the substrate and the adhesive is cured to encapsulate the device. By partially curing the adhesive prior to mounting the cap, the curing of the adhesive can be achieved without prolonged exposure to UV radiation or high temperatures which can adversely impact the device.

Abstract: An IC with memory cells arranged in groups is described. The memory cells, for example, are ferroelectric memory cells. The IC includes a variable voltage generator (VVG) for generating an output voltage having a different voltage level depending on a location of an addressed memory cell within the memory group is provided. By providing different voltage levels for reads and/or writes, signal loss caused by capacitances which is dependent on the location of the memory cell within the group can be avoided. This improves read and/or write operations in series memory architectures.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The access transistors are high gate threshold voltage transistors to reduce leakage current in the memory cell. The gate threshold voltage of the access transistors are, for example, 0.1 to 0.4V higher than typical transistors. Reducing leakage current advantageously improves the retention time of the memory cell.

Abstract: An improved memory architecture is described. The memory architecture includes separately controlled refresh and sense amplifiers to enable a memory access and refresh cycle simultaneously.

Abstract: A capacitor with improved reliability is disclosed. The capacitor includes a bottom electrode, a top electrode, and an intermediate layer therebetween. A contact, which is electrically coupled to the top electrode, is provided. At least a portion of the contact is offset from the capacitor. By offsetting the contact from the top electrode, the etch damage to the top electrode is reduced, thereby reducing or eliminating the need for the anneal to repair the etch damage.

Abstract: In an IC having memory cells, a write operation is performed on a word within a particular row of memory cells. The other words within the same row are refreshed during the same cycle. In another embodiment, dual port memory cells are employed to enable a second row of memory cells to be refreshed during the same cycle.

Abstract: A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A plurality of delayed state cycles is generated from the clock signal for clocking internal operations within the clocked integrated circuit.

Abstract: A capacitor over plug (COP) structure is disclosed. The COP avoids the step which is created in conventional COP structures, which adversely impacts the properties of the capacitor. In one embodiment, the step is avoided by providing a plug having upper and lower portions. The upper portion, which is coupled to the bottom electrode of the capacitor, has substantially the same surface area as the bottom electrode. A barrier layer can be provided between the plug and bottom electrode to avoid oxidation of the plug material.

Abstract: A memory cell which provides a diffusion path for hydrogen to the transistor is disclosed. The diffusion path is provided by forming a contact in which the upper section overlaps the lower section, thus creating a gap that serve as a hydrogen diffusion path. The hydrogen diffusion path is necessary for annealing the damage to the gate oxide.

Abstract: A software programmable fuse cell which reduces or eliminates static power consumption is disclosed. The programmable fuse cell includes programmable and non-programmable operating modes. Depending on the operating mode, the fuse cell output is determined by the actual state of the fuse or which fuse state the fuse cell is simulating. To reduce static power consumption, a latch is used to store the actual or simulated fuse state.

Abstract: An improved barrier stack for reducing plug oxidation in capacitor-over-plug structures is disclosed. The barrier stack is formed on a non-conductive adhesion layer of titanium oxide. The barrier stack includes first and second barrier layers wherein the second barrier layer covers the top surface and sidewalls of the first barrier layer. In one embodiment, the first barrier layer comprises Ir and the second barrier layer comprises IrOx. Above the barrier stack is formed a capacitor.

Abstract: A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.

Abstract: A memory cell is provided with a first access transistor coupled to a first terminal of the storage transistor and a second access transistor coupled to a second terminal of the storage transistor is disclosed. The gates of the access transistors are coupled to word lines. In the inactive state, the word lines comprise a negative voltage to reduce leakage current from the memory cell.

Abstract: A memory cell having a plurality of first access transistors are coupled to a first terminal of the storage transistor and a second access transistors coupled to a second terminal of the storage transistor is disclosed. The access transistors serve as access ports for the memory cell.

Abstract: A memory cell having first and second access transistors coupled to a storage transistor is disclosed. The storage transistor comprises a gate oxide formed from a material having a high dielectric constant to increase the capacitance.