Abstract: The invention pertains to a layout for a semiconductor memory with multiple memory cells. The layout according to this invention takes into account the “design rules” specified by the manufacturing process or those required by the technology, and attempts to optimize the surface area of the layout of the semiconductor memory. The particular advantage of the invention rests in the fact that for each memory cell, effectively only one contact terminal is needed. In this manner, the required surface area for the semiconductor memory can be reduced significantly. Due to the reduction in the number of contact terminals, the leakage currents can also be reduced.

Abstract: A method is described for the selective deposition of bismuth based ferroelectric films by selective chemical vapor deposition on a substrate. Selectivity in the deposition process is attained by selection of substrate-precursor combinations which assure high bismuth deposition efficiency in certain areas and low bismuth deposition efficiency in other areas in combination with specific process parameters.

Abstract: A method for replacing defective elements of a memory array. The method includes forming a first redundant circuit, which in turn includes forming a first plurality of address fuses. The first plurality of address fuses are configured to specify, when set, an address of one of the defective elements. The method further includes forming a first plurality of address latches, respective ones of the first plurality address latches being coupled with respective ones of the first plurality of address fuses. There is further included forming a first redundant element. Additionally, the method includes forming a first decoding logic circuit. The first decoding logic is coupled to the first plurality of address latches and the redundant element.

Abstract: A method and apparatus for forming a multi-constituent device layer on a wafer surface are disclosed. The multi-constituent device layer is formed by flowing a first chemistry comprising a first constituent and a second chemistry comprising a second constituent via a segmented delivery system into a reaction chamber. The reaction chamber comprises a susceptor for supporting and rotating the wafers. The segmented delivery system comprises alternating first and second segments into which the first and second chemistries, respectively, are flowed. The first segments comprise an area that is greater than an area of the second segments by an amount sufficient to effectively reduce the diffusion path of the first constituent. Reducing the diffusion path of the first constituent results in a more uniform distribution of the first constituent within the device layer.

Abstract: Method for forming three-dimensional device structures comprising a second device formed over a first device is disclosed. A layer having a single crystalline top surface is formed above the first device to provide the base for forming the active area of the second device.

Abstract: Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.

Abstract: A programmable fuse element disposed between integrated circuit elements that may be selectively joined during the manufacture or programming of an integrated circuit. The fuse element is a normally open fuse that electrically isolates the integrated circuit elements. The fuse element is comprised of a central area of conductive material insulated from the integrated circuit elements by areas of dielectric material. The integrated circuit elements and the fuse element are disposed on a thin oxide layer covering a semiconductor substrate to prevent those elements from shorting to the semiconductor substrate or to each other via the semiconductor substrate. A protective dielectric layer may be deposited over both the fuse element and the integrated circuit elements during the manufacture of the overall integrated circuit. A laser beam is used to burn through the protective layer and melts both the conductive material and the dielectric material that form the fuse element.

Abstract: A method for allowing the removal of a TEOS etch mask layer utilizing an anisotropic technique such as reactive ion etching. The use of the anisotropic technique results in substantially less undercutting of the pad oxide layer than wet chemical etching techniques. One embodiment of the invention involves forming a polysilicon etch stop layer under the pad TEOS layer.

Abstract: A fuse bank for use in the laser break-link programming of an integrated circuit device. The fuse bank uses fuse elements with two ends that contain fusible regions proximate the first end and non-fusible regions proximate the second end. The fuse elements are aligned in alternately oriented parallel rows so that the first end of each fuse element is juxtaposed with the second end of any adjacent fuse element. By sequentially alternating the orientation of the fuse elements in the fuse bank, the fuse elements can be formed in a highly dense matter without bringing any two fusible regions too close to one another. Accordingly, a laser can be used to sever selected fusible regions without adversely effecting other fusible regions within the fuse bank. By alternating the orientations of sequential fuse elements, a fuse bank can be created that is twice as dense as single orientation fuse banks with only a 30% to 50% increase in size.

Abstract: A process for ablation etching through one or more layers of dielectric materials while not etching an underlying conductive material layer comprises selecting parameters whereby the ablation process automatically stops when the conductive material layer is reached, or monitoring the process for end point detection of the desired degree of ablation. Parameters selected are the absorptivity of the dielectric layer versus that of the conductive material layer. End point detection comprises monitoring radiant energy reflected from the workpiece or the content of the materials being ablated from the workpiece.

Abstract: A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

Abstract: New types of apertures to vary the size and shape of the aperture area without the need to change the whole aperture plate in off axis lithography. The off axis illumination apertures allow the size and shape of apertures to be changed without having to change the aperture plates for each step in the lithographic process. The aperture plate is fitted with simple shutter mechanisms that allow the ready adjustment of the aperture openings.

Abstract: The present invention phase shifting photomask is fabricated by means of a structured modification to the surface of a mask blank suitable for photolithography. Ion implantation, diffusion or similar processes are used to alter the optical properties of selected areas of a mask blank in such a way that these areas modify the intensity and phase of optical radiation transmitted through the processed areas of the mask blank substrate. The present invention provides the intended phase and intensity modulation by modification of a surface layer or other layer which is close to the surface of the mask blank. This leaves the actual surface of the mask blank intact and smooth without chemical changes to the surface of the mask blank. In this way optical radiation is not scattered on the borders of different materials and unwanted particulates will have a lower chance of adhering to a smooth surface with little or no topography.

Abstract: An improved trench cell capacitor for a memory cell and process for fabricating the same. The process includes the steps of forming a trench within a semiconductor body; forming a dielectric layer peripherally within the trench and filling at least a portion of the trench by epitaxially growing semiconductor material therein. The epitaxially grown semiconductor material is void and seam-free, resulting in a robust trench cell that is highly reliable, thereby improving process yield.

Abstract: A method of fabricating sub-GR gates in a deep trench DRAM cell. The method comprises depositing, removing, and selectively etching a plurality of layers which include sacrificial spacers, liners, masking, and resist layers of both semiconducting and non-semiconducting materials on a semiconductor substrate according to specific process flows designed to circumvent the problems associated with prior art sub-GR processes. The method represents an improvement on standard gate conductor processes and provides a device which achieves an up to now unachieved decoupling of channel doping and junction doping.

Abstract: An apparatus and associated method for removing microscopic particle contaminants from an object such as a photomask or a semiconductor wafer. The apparatus utilizes an inspection device to identify the position of any particle contaminants on the target object. Once the positions of the various particle contaminants has been identified, a probe is dispatched to the position of one of the particle contaminants. The probe removes the particle contaminant from the target object and moves to a cleaning compartment, wherein the particle contaminant is removed from the probe. The probe is then moved to the next subsequent particle contaminant until all the contaminants are removed from the target object. By removing particle contaminants one-by-one from the target object, the manufacturing yield of zero defect products is greatly increased.

Abstract: A deep trench DRAM cell is formed on a silicon on isolator (SOI) substrate, with a buried strap formed by outdiffusion of dopant in associated trench node material, for providing an electrical connection between the trench node and the active area of a MOS transfer gate formed in the substrate adjacent the trench in an uppermost portion of the substrate.

Abstract: Electronic devices having at least two components with mating contact pads are provided with high-aspect-ratio solder joints between the mating pads. These joints ar formed by placing a composite solder medium containing solder wires in an electrically insulating matrix such that at least two solder wires are in contact with the mating pads, and fusing the wires to the pads. The insulating matrix with remainder of solder wires is then optionally removed from between the said at least two components. The composite solder medium is formed by preparing an elongated body of solder wires in an insulating matrix and cutting off slices of the composite solder medium, the solder wires having a high-aspect-ratio of length to their diameter. Alternatively sheets of the composite solder medium are prepared by magnetically aligning solder coated magnetic particles into columns arranged transverse of an insulating matrix and heating sufficiently to fuse the solder in each column into a continuously conducting solder path.

Abstract: Pb-free solder alloys based on the Sn-In-Zn system (exemplarily 86:5:9 weight %) are disclosed. Compositions can have a melting temperature in the range 183.degree. C..+-.10.degree. C. and thus can be readily substituted for conventional 40 Pb-60 Sn solder. The novel compositions also can possess superior mechanical properties, compared to the 40/60 Pb-Sn composition, and readily wets copper. Bi and/or Sb may be added to the Sn-In-Zn base to reduce the tendency for the formation of lower temperature phases.

Abstract: Electronic devices having at least two components wire mating contact pads are provided with high-aspect-ratio solder joints between the mating pads. These joints ar formed by placing a composite solder medium containing solder wires in an electrically insulating matrix such that at least two solder wires are in contact with the mating pads, and fusing the wires to the pads. The insulating matrix with remainder of solder wires is then optionally removed from between the said at least two component. The composite solder medium is formed by preparing an elongated body of solder wires in an insulating matrix and cutting off slices of the composite solder medium, the solder wires having a high-aspect-ratio of length to the diameter. Alternatively sheets of the composite solder medium are prepared by magnetically aligning solder coated magnetic particles into columns arranged transverse of an insulating matrix and heating sufficiently to fuse the solder in each column into a continuously conducting solder path.