Patents Represented by Attorney Diane C. Drozenski
  • Patent number: 5923863
    Abstract: Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine if the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of an eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handling routine if the semaphore indicates that an exception occurred when said speculative instruction was executed, and the predicate is true, which indicates that said speculative instruction was properly executed.
    Type: Grant
    Filed: October 25, 1995
    Date of Patent: July 13, 1999
    Assignee: Digital Equipment Corporation
    Inventors: Michael C. Adler, Steven O. Hobbs, Paul Geoffrey Lowney
  • Patent number: 5870590
    Abstract: A system and apparatus for generating an extended finite state machine (EFSM) from a specification expressed as a set of data relationships. The specification is written in a specification language designed for the purpose, and is parsed in a conventional fashion. The parsed specification is used as input to the method of the invention, which comprises routines for transforming it into an EFSM including states and transitions. The EFSM thus generated is used as input to a traversal procedure, for ultimately generating validation tests to verify the operation of an implementation of the specification, with one such test being generated for each path traversed through the EFSM. The traversal of the EFSM may be carried out in a conventional fashion or by using applicant's EFSM traversal method. The EFSM's transitions represent functions and test information, and the states represent the status of the EFSM at particular points, given the traversal of a particular path through the EFSM, i.e.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: February 9, 1999
    Inventors: Ronald Allen Kita, Mark Edward Trumpler, Lois Scirocco Elkind
  • Patent number: 5825679
    Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: October 20, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Gilbert M. Wolrich, Andrew S. Olesin
  • Patent number: 5819064
    Abstract: A new class of purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.
    Type: Grant
    Filed: November 8, 1995
    Date of Patent: October 6, 1998
    Assignees: President and Fellows of Harvard College, Digital Equipment Corporation
    Inventors: Rahul Razdan, Michael D. Smith
  • Patent number: 5812763
    Abstract: A new security system including a plurality of inspectors each of which performs a security check operation in connection with a particular class of possible security violation conditions. One inspector detects security violation conditions reflecting selection of passwords using easily-guessable formatives. Another inspector detects security violation conditions reflecting ability of a network node to improperly use another node over a network. A third inspector determines whether the operating system files have satisfactory protection. Finally, a fourth inspector determines whether security violation conditions arise in connection with applications programs. If, during a security check operation, an inspector determines that a security violation condition exists, it records the condition in a common working memory for further reporting or analysis.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: September 22, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Henry Shao-Lin Teng
  • Patent number: 5802373
    Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.
    Type: Grant
    Filed: January 29, 1996
    Date of Patent: September 1, 1998
    Assignee: Digital Equipment Corporation
    Inventors: John S. Yates, Stephen C. Root
  • Patent number: 5796976
    Abstract: Information is stored in temporary storage and subsequently transferred to a memory over a bus. The temporary storage is provided with a plurality of entries each of which has a selected size that is smaller than a size of the bus. Information that is designated for a common area of the memory is stored in different entries, and the different entries are linked. Before being transferred to memory, the information from linked entries is assembled. The assembled information is then transferred over the bus to memory. Embodiments of the temporary storage include a write queue and a write buffer.
    Type: Grant
    Filed: January 23, 1996
    Date of Patent: August 18, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Bhavin Shah, Era Nangia, Gilbert Wolrich, Nital Patwa
  • Patent number: 5797023
    Abstract: An apparatus is described to provide a fault tolerant power-on of a computer system, using a BIOS memory containing a primary power-on system level configuration program for a computer system and a separate memory which contains a subset of the primary power-on system level configuration program. The subset program is accessed automatically, without human intervention, responding to a checksum detector of the BIOS memory data.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: August 18, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Rachael Berman, Stephen F. Shirron, Fidelma Hayes, Kevin Peterson, Marco Ciaffi
  • Patent number: 5778423
    Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: July 7, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Richard Lee Sites, Richard T. Witek
  • Patent number: 5774727
    Abstract: A language construct that allows a software programmer to use an intermediate or high-level language command to explicitly group operations or fuse loops in a group of statements operating on parallel arrays is disclosed. The command instructs a compiler, which would otherwise add temporary variables to avoid data dependencies or perform data dependency analysis, to translate the enclosed statements directly into machine language code without adding those temporary variables and without performing any data dependency analysis. Execution of the command results in the performance of the group of statements by all of the virtual processors.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: June 30, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Robert J. Walsh, Bradley Miller
  • Patent number: 5765193
    Abstract: A data storage system includes a multi-tasking processor which manages a write cache to identify adjacent blocks held in the write cache which are to be included in a next write operation, while at the same time handling data transfer requests from a system host. The processor monitors the write cache and when the cache has fewer than a predetermined number of storage locations free, initiates a block-merge task. The processor then determines which block in the write cache is least recently used and, based on virtual block numbers assigned to the data blocks, identifies the blocks in the write cache which are adjacent to the least recently used block and are within the same chunk as that block. The processor maintains a list of these adjacent blocks and the locations in which the blocks are held in the write cache.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: June 9, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Mitchell N. Rosich, Eric S. Noya, Jeffrey T. Wong
  • Patent number: 5742537
    Abstract: A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: April 21, 1998
    Inventors: Gilbert M. Wolrich, Timothy C. Fischer, John J. Ellis, Patricia L. Kroesen
  • Patent number: 5742746
    Abstract: A terminal, such as character display unit or printer, has a character pattern memory region. A host system controls an operation of outputting a character to the terminal. In case of outputting a desired character to the terminal, firstly an examination is made at the side of the host system as to whether or not a character pattern corresponding to the desired character is stored in the character pattern memory region. When it is determined that the character pattern has not been stored in the character pattern memory region, the character pattern from the host system is loaded into the character pattern memory region.
    Type: Grant
    Filed: November 24, 1992
    Date of Patent: April 21, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Hitoshi Doi, Masayoshi Okutsu
  • Patent number: 5740357
    Abstract: A method of managing faults in a computer system including the steps of detecting an error, handling the error along a functional hierarchy and, further, handling a fault that caused the error in a management hierarchy which can be operated separately from the functional hierarchy.
    Type: Grant
    Filed: October 26, 1994
    Date of Patent: April 14, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Jeffrey L. Gardiner, Gerhard K. Heider, Larry W. Emlich, Bruce H. Luhrs, Michael C. Li, Michael R. Masters, Russell Lloyd Myers, Harlo A. Peterson, Frank M. Robbins, Mark J. Seger
  • Patent number: 5729485
    Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: March 17, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Gilbert M. Wolrich, Sribalan Santhanam, Andrew S. Olesin
  • Patent number: 5726927
    Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: March 10, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Gilbert M. Wolrich, John A. Kowaleski, Jr.
  • Patent number: 5717729
    Abstract: A remote delay regulator circuit measures the effects of intrinsic propagation delays experienced by a system clock signal propagating through an extended clock distribution path that encompasses a clock repeater chip, a module transmission network and a clock distribution network of an integrated circuit (IC) chip. Delay measurement of the associated (IC) chips on the module is provided by sensing the clock signal at the beginning of the network and at the end of the network. The BEFORE and AFTER sense taps are routed to a signal generation circuit on the repeater chip where measurement signals are generated that define the beginning and end of a measurement cycle. A clock delay path circuit on the repeater chip contains the logic circuitry required to measure and compensate for the actual measured intrinsic propagation delays of the total clock transmission network.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: February 10, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Russell Iknaian, Richard B. Watson, Jr.
  • Patent number: 5694350
    Abstract: A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: December 2, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Gilbert M. Wolrich, Timothy C. Fischer, John A. Kowaleski, Jr.
  • Patent number: 5694579
    Abstract: Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the logic design being subject to resistive conflicts and to charge sharing, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. A three-state version of simulation code is generated for the circuit design, the three states corresponding to states 0, 1, or X, where X represents an undefined state. A preanalysis was performed of the three-state version and phase waveforms are stored each representing values occurring at a node of the code. For each phase of a module for which no event-based evaluation need be performed, an appropriate response to an event occurring with respect to the module of the three-state version is determined and stored.
    Type: Grant
    Filed: February 18, 1993
    Date of Patent: December 2, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Rahul Razdan, Gabriel Bischoff
  • Patent number: 5687310
    Abstract: An apparatus which provides a means of ensuring command synchronization for computer systems employing sliced gate array processors includes a computer bus, a plurality of central processing units and a plurality of input/output processors coupled to the computer bus. Each input/output processor includes means to receive commands from said central processing units. The apparatus further includes means within each of the input/output processors for generating a signal indicating the type of command received from the central processing units and means for receiving from every other input/output processor the command type signal generated by every other input/output processor. In addition, the apparatus further includes means for comparing said command type signals and generating an error signal when the comparison indicates that all of the input/output processors have not received the same command.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: November 11, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Paul Stuart Rotker, Randall Dean Hinrichs