Abstract: A ferroelectric memory arrangement having memory cells, in each of which a vertical ferroelectric storage capacitor, which includes vertical electrodes and a ferroelectric dielectric between the vertical electrodes, is connected to a select transistor, the ferroelectric dielectric a plurality of ferroelectric layers, between each of which is arranged an insulating separating layer.
Type:
Grant
Filed:
August 31, 2005
Date of Patent:
March 25, 2008
Assignee:
Infineon Technologies AG
Inventors:
Rainer Bruchhaus, Martin Gutsche, Cay-Uwe Pinnow