Abstract: A semiconductor component suitable for use as a power semiconductor component and method of making a semiconductor component is disclosed. In one embodiment, the semiconductor component includes a semiconductor body having a first surface, a second surface, a third surface, a first conduction type region and a second conduction type region adjoining the first conduction type region at the third surface. A trench extending from the first surface into the semiconductor body, the trench defined by a trench bottom and an arcuately shaped sidewall.

Abstract: A storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.

Abstract: To store information in a ferroelectric material, a sample probe is used to bring about mechanical action on individual domains and thereby to cause a reversal of polarization in the individual domains, with electrodes situated below the ferroelectric material being able to have a bias applied to them to stabilize the change/reversal of polarization. The reversal of polarization causes an alteration in the surface topography of the ferroelectric material, and this alteration can be used to read the information. The stored information is therefore obtained by ascertaining the surface topography of the ferroelectric material. The information is written and read using an AFM tip, with the tip being able to be operated in contact or tapping mode for the purpose of writing, and additionally in noncontact mode for the purpose of reading.

Abstract: A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.

Abstract: A memory cell is provided which comprises two electrodes and a layer arranged in between and comprising an active material comprising (a) a compound selected from the group consisting of in which R1 and R4, independently of one another, may have the following meaning: —H, -alkyl, -aryl, -heteroaryl, —O-alkyl, —O-aryl, —O-heteroaryl, —SH, —S-alkyl, —S-aryl, —S-heteroaryl, —CO-alkyl, —CO-aryl, —CO-heteroaryl, —CS-alkyl, —CS-aryl, —CS-heteroaryl, -halogen, —CN and/or —NO2, in which R1 and R2, R2 and R3, R3 and R4 together may form a ring, (b) a compound of the general formula II: in which R5 to R7, independently of one another, may have the following meaning: —H, -alkyl, -aryl, -heteroaryl, —O-alkyl, —O-aryl, —O-heteroaryl, —NH2, —N(alkyl)2, —N(aryl)2, —N(heteroaryl)2, —SH, —S-alkyl, —S-aryl, —S-heteroaryl, —CO-alkyl, —CO-aryl, —CO-heteroaryl, —CS-alkyl, —CS-aryl, —CS-heteroaryl, -halogen, —CN and/or —NO2, in which R5 and R6 or R7 and R8 together may form a ring, and optionally (c) a polymer.

Abstract: A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material into the isolation material.