Abstract: A clock controller for use with an off-chip driver and including a first delay element, a second delay element, a restore circuit, and an adjustment circuit. The clock controller includes a node receiving a reference clock represented by a least one clock signal. The first delay element is configured to delay one of the at least one clock signals by a first delay time, and the second delay element is configured to delay one of the at least one clock signals by a second delay time. The restore circuit is configured to provide at least a first output clock to the off-chip driver, wherein the off-chip driver provides output data based at least on the first output clock. The adjustment circuit is configured to adjust the first and second time delays to adjust edges of the first output clock such that output data from the off-chip driver aligns with edges of the reference clock, and to adjust the second delay time to maintain the first output clock at a desired duty cycle.

Abstract: An input circuit including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal and a second signal and to sample the first signal via the second signal and provide signal samples of the first signal. The second circuit is configured to receive a third signal and the signal samples and to update a second circuit output signal via the third signal and provide the updated second circuit output signal. The third circuit is configured to receive a clock signal and the second signal and to provide the third signal. The third circuit is also configured to synchronize edges in the third signal to edges in the second signal and edges in the clock signal.

Abstract: The present invention provides a single-event upset (SEU) hardened integrated circuit. The integrated circuit includes an SEU hardened asymmetric bi-stable CMOS latch having a first logic state and a second logic state. A supply voltage is operably coupled to the asymmetric bi-stable latch, where upon activation of the supply voltage the asymmetric bi-stable latch is always set to the first logic state. A switch may be provided for changing the latch from the first logic state to the second logic state.

Abstract: A method of detecting a break in a transfer line transporting a fluid product between a first vessel and a second vessel includes sensing a current pressure of fluid product associated with the transfer line. A highest sensed pressure of the fluid product is continually tracked, and a trip pressure is defined. The trip pressure increases to new multiple value(s) at any or many of a possible multiple number of times when the highest sensed pressure increases. The method further includes detecting when the current sensed pressure drops below the trip pressure to detect a break in the transfer line, via use of a pressure sensor in or in fluid communication with the transfer line. A method of automatically shutting off transfer of fluid product between a first vessel and a second vessel includes a step for shutting off the transfer of fluid product between the first vessel and the second vessel.

Abstract: A data storage tape cartridge having a reinforcing tape reel lock. The data storage tape cartridge includes a housing defined by a first housing section and a second housing section, a hub pin extending from an interior surface of the first housing section, a tape reel assembly rotatably maintained by the hub pin and a storage tape wrapped about the tape reel assembly. The tape reel assembly includes a hub, opposing tape flanges and a brake body. The hub includes a tape receiving portion interiorly secured to a post, the post defining an axial bore sized to receive the hub pin. The brake body is retractably associated with an axial end of the hub and includes a braking surface and an interior support surface. The braking surface is configured for selective engagement with the second housing section. The interior support surface is configured to abut the post of the hub.