Abstract: A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.

Abstract: A method and system that uses an anticipatory signal to pre-adjust the output of the power supply to compensate for an upcoming load change, thereby minimizing the voltage deviation at the load. A control circuit, such as a processor, controlling the system generates an anticipatory signal indicating an upcoming change in the load that is input to the power supply. The power supply, in response to the signal from the processor, adjusts the output of the power supply accordingly to compensate for the upcoming load change. When the system performs the operation that results in the load change, the power supply output has already been adjusted accordingly and the deviation of the load voltage caused by the change in the load is minimized.