Patents Represented by Law Firm Dickstein, Shaprio & Morin
  • Patent number: 7018596
    Abstract: Accordingly, the invention provides: (1) mesoporous silica characterized by having an average pore diameter in the mesopore region of from 1.5 to 10 nm, a nitrogen adsorption specific surface area determined by the BET method of from 500 to 1400 m2/g, and a monolayer adsorption of water at 25° C. of 1.7 H2O molecules/nm2 specific surface area or more; (2) a process for synthesizing the mesoporous silica characterized by mixing and reacting active silica with a neutral template and removing the neutral template from the thus formed complex; (3) ink absorbents characterized by containing mesoporous silica; (4) ink absorbent slurries composed of the above-described ink absorbent and a solvent; and (5) recording sheets characterized by containing the above-described ink absorbent.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: March 28, 2006
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventors: Seiji Satou, Tadashi Shimizu
  • Patent number: 6990041
    Abstract: A memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: January 24, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Christopher S. Johnson, Scott Schaefer
  • Patent number: 6956861
    Abstract: An interconnect structure comprising a plurality of input ports and a plurality of output ports with messages being sent from an input port to a predetermined output port through a switch S. Advantageously, the setting of switch S is not dependent upon the predetermined output port to which a particular message is being sent.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: October 18, 2005
    Assignee: Interactics Holdings, LLC
    Inventors: Coke Reed, David Murphy
  • Patent number: 6955940
    Abstract: A method of forming a non-volatile resistance variable device includes forming a first conductive electrode material on a substrate. A metal doped chalcogenide comprising material is formed over the first conductive electrode material. Such comprises the metal and AxBy, where “B” is selected from S, Se and Te and mixtures thereof, and where “A” comprises at least one element which is selected from Group 13, Group 14, Group 15, or Group 17 of the periodic table. In one aspect, the chalcogenide comprising material is exposed to and HNO3 solution. In one aspect the outer surface is oxidized effective to form a layer comprising at least one of an oxide of “A” or an oxide of “B”. In one aspect, a passivating material is formed over the metal doped chalcogenide comprising material. A second conductive electrode material is deposited, and a second conductive electrode material of the device is ultimately formed therefrom.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: October 18, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Kristy A. Campbell, Terry L. Gilton, John T. Moore, Jiutao Li
  • Patent number: 6918965
    Abstract: A device for magnetically annealing magnetoresistive elements formed on wafers includes a heated chuck and a delivery mechanism for individually placing the wafers individually on the chuck one at a time. A coil is adjacent to the chuck and generates a magnetic field after the wafer is heated to a Néel temperature of an anti-ferromagnetic layer. A control system regulates the temperature of the heated chuck, the strength of the magnetic field, and a time period during which each chuck is heated to control the annealing process. The annealed elements are incorporated in the fabrication of magnetic memory devices.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: July 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Mark E. Tuttle, Ronald A. Weimer
  • Patent number: 6830305
    Abstract: A high-quality gray scale printing is attained by using an ink jet recording head having a simple and low-cost configuration and a general-purpose structure, and ink having common components. An ink jet recording head driving method to be disclosed comprises repeating a plurality of times a dot forming process for forming a plurality of dots on a recording medium, while an ink jet recording head is moved in a sub-scanning direction; the process comprising the steps of moving the ink jet recording head in a main scanning direction, generating a plurality of drive waveform signals according to a jet amount of ink droplets, selecting any one or none of the plurality of waveform signals for each of a plurality of nozzles according to gray scale information of printing data, and applying voltage to corresponding piezolectric actuators.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: December 14, 2004
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Fuminori Takizawa
  • Patent number: 6748206
    Abstract: A radio receiver includes a device for decreasing the data rate of reception data in accordance with the channel frequency of the reception data, and a device for performing signal processing for the reception data whose data rate has been decreased.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: June 8, 2004
    Assignee: NEC Corporation
    Inventor: Mariko Matsumoto
  • Patent number: 6740870
    Abstract: A photosensitive chip element is mounted in a totally clear package. The incoming fight can pass through the package at any angle. The incoming light passed through the package is sensed by the photosensor and converted to a signal indicative thereof. Since the package is clear, no special way of mounting the chip is necessary.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: May 25, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Nicholas A. Doudoumopoulos
  • Patent number: 6636559
    Abstract: A channel response estimation circuit is provided that can estimate a channel longer than a correlation code sequence length. The pattern detection circuit 103 detects a symbol pattern corresponding to an estimated channel length. An inverse matrix for correction corresponding to the detected symbol pattern is input to the correlator-output correction circuit 107. The estimation range selection circuit 105 determines the estimation range. A channel longer than the correlation code sequence length can be estimated by multiplying the correlator-output corresponding to an estimation range selected in the correlator-output correction circuit 107 by the inverse matrix for correction.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: October 21, 2003
    Assignee: NEC Corporation
    Inventor: Yoshikazu Kakura
  • Patent number: 6606000
    Abstract: A radio-frequency amplifier comprises slot lines formed in a top electrode which are bent to define matching segments that are perpendicular to transmitting segments. The matching segments have a length corresponding to one-quarter of the wavelength of a signal to be amplified and are at least partially perpendicular to the transmitting segments. A DC-cut circuit comprising slot lines is connected to the matching segments, an FET is connected to the transmitting segments and the matching segments, and respective matching circuits serve as an input unit and an output unit of the FET. Source terminals of the FET are connected to parts of a top electrode that do not lie between the segments. A drain terminal and a gate terminal are connected, to be electrically separated from each other, to parts of the top electrode, which are electrically separated from the source terminals by the DC-cut circuit, the transmitting segments, and the matching segments.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: August 12, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeyuki Mikami, Takatoshi Kato, Hiroyasu Matsuzaki
  • Patent number: 6592152
    Abstract: The present invention relates to a joint structure between a filtration apparatus and a filtration membrane module, which is characterized in that a cap with a pipe is disposed on at least one end of a filtration membrane module using a cap nut capable of being screwed into a thread groove formed on the outer periphery of the end thereof, said pipe of the cap being inserted into and pressed against one end of a joint capable of controlling connection length at both ends, and a branch pipe of a header pipe of the filtration apparatus being inserted into and pressed against the other end of said joint. According to the present invention, there can be obtained such a joint structure that requires fewer components for connection, has a simple construction at connections, and does not cause any leakage.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: July 15, 2003
    Assignee: Asahi Kasei Corporation
    Inventors: Tatsuo Nejigaki, Nobuhiko Suga
  • Patent number: 6590475
    Abstract: A filter with which it is possible to control the relationship between a pass band and an attenuation band. In this filter, for example, a single-stage trap filter is electrically connected to a three-stage band pass filter via a coupling capacitor. The trap filter has a serial resonance section composed of a resonator and a resonance capacitor. The serial resonance section is connected in parallel to a capacitive reactance element (capacitor), and a serial circuit composed of an inductive reactance element (inductor) and a PIN diode as a switching element. The capacitive reactance element and the inductive reactance element both serve to make an admittance of the trap circuit substantially zero.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: July 8, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuo Yamada, Kikuo Tsunoda, Masayuki Atokawa, Hirofumi Miyamoto, Hajime Suemasa
  • Patent number: 6573809
    Abstract: A compact dielectric resonator device that permits reduction in size of a metal cover without deterioration of the filter characteristics of the device. In this dielectric resonator device, a plurality of dielectric coaxial resonators are mounted on a substrate. A metal cover is arranged in such a manner as to enclose substantially only the open faces of the dielectric coaxial resonators, where terminals electrically connected to inner conductors of the dielectric coaxial resonators are led out. In addition, protrusions of the metal cover are electrically connected to parts of the outer conductors of the dielectric resonators between the adjacent dielectric coaxial resonators.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: June 3, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tsutomu Wakayama, Takashi Maruyama
  • Patent number: 6425032
    Abstract: The invention concerns an arbitration scheme for permitting access to the bus of a computer. The arbitration scheme has the ability to control and reduce the delay experienced by any device by monitoring the queue length of the device and using information concerning the device, such as device rate, phase, data transfer size and queue length. Specifically, the arbiter prevents periodic accessing devices, such as audio and video samplers, from being delayed or interrupted for long periods of time once they have begun accessing the bus.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: July 23, 2002
    Assignee: Lucent Technologies Inc.
    Inventor: G. N. Srinivasa Prasanna
  • Patent number: 6200909
    Abstract: The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective layers without etching excessive amounts of an underlying oxide.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: March 13, 2001
    Assignee: Micron Technology Inc.
    Inventors: Kevin James Torek, Whonchee Lee, Satish Bedge
  • Patent number: 6154418
    Abstract: A double data rate (DDR) synchronous dynamic random access memory (SDRAM) device with at least one memory bank is disclosed. Each memory bank is divided into two independent and simultaneously accessible memory planes. Input data aligned with the rising edge of a data strobe (DQS) and input data aligned with the falling edge of the DQS are separately latched coincident with the respective edges of the DQS. Using an internal clock, the latched input data is re-aligned and simultaneously sent to both planes of an addressed memory bank at the rising edge of the internal clock. With this configuration, the internal processing of the SDRAM is unaffected by latency variations of the DQS.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: November 28, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Wen Li
  • Patent number: 6032264
    Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: February 29, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Ray J. Beffa, William K. Waller, Lee R. Nevill, Warren M. Farnworth, Eugene H. Cloud
  • Patent number: 5639119
    Abstract: Disclosed herein is a vehicle including a frame, and a stabilizer apparatus including a pressure source, first and second fluid-actuated stabilizer assemblies connected respectively to the front and rear axles shiftably moveable on the frame, one of the first and second stabilizer assemblies normally being locked against extension and contraction in the absence of pressurization thereof by the pressure source, and the other of the first and second stabilizer assemblies normally being free to extend and contract in the absence of pressurization thereof by the pressure source, a hydraulic circuit connected between the pressure source and the first and second fluid activated stabilizer assemblies and including a flow controller operable between a first mode wherein the pressure source is disconnected from the first and second stabilizer assemblies, whereby the one of the stabilizer assemblies is locked against extension and retraction, thereby locking the axle connected thereto against shifting movement relative
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: June 17, 1997
    Assignee: Trak International, Inc.
    Inventors: John R. Plate, J. Scott Bargenquast, Terry A. Weber
  • Patent number: 5150420
    Abstract: A signature identification system includes an IC card having a memory storing sign data representing a genuine signature and a display device for displaying the genuine signature by readign the sign data stored in the IC card. A writing unit includes a sign reading device for reading a genuine signature signed by an authorized person and a writing device for writing data representing the read genuine signature on an IC card, whereby the genuine signature is invisibly stored in the IC card and imitation of the genuine signature by viewing the genuine signature in the card can be avoided.
    Type: Grant
    Filed: June 18, 1991
    Date of Patent: September 22, 1992
    Assignee: Omron Tateisi Electronics Co.
    Inventor: Kaoru Haraguchi
  • Patent number: D314839
    Type: Grant
    Filed: October 12, 1988
    Date of Patent: February 19, 1991
    Assignee: Windmere Corporation
    Inventor: Elizabeth Ho