Abstract: A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts operations received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units.

Abstract: A method, computer program product, and data processing system for efficiently diagnosing errors and inefficiencies in database application code are disclosed. According to a preferred embodiment, techniques of aspect-oriented programming (AOP) are used to instrument database application code to monitor the usage of database resources. Specifically, pointcuts are defined to intercept accesses of database resources. Advice code associated with these pointcuts is used to collect information about the usage of database resources and to detect certain errors, such as resource leaks, when they occur. In a preferred embodiment, the AspectJ aspect-oriented programming language/system is used to define the pointcuts and advice code.

Abstract: A method and system for sampling video data uses re-sampling filters having lengths optimized relative to a quantization parameter of video processing. The method uses modeling of an optimal length of the re-sampling filter as a function of the quantization parameter to derive empirical formulas and a look up table for optimal lengths of re-sampling filters. The resulting re-sampling filters are selectively adapted for sampling video data having different bit rates.

Abstract: Multiple autonomous intelligent Remote Terminal Units (RTUs) are positioned on distribution lines in an electrical power grid. The intelligent RTUs perform analytics on power flowing through the distribution lines to provide real-time analysis of the power. The intelligent RTUs acquire sensor data from the distribution lines and locally perform the analytics on the sensor data to create processed data signals that are transmitted to a control center server to facilitate power distribution monitoring of the electrical power grid.

Abstract: The inventive method includes creating a first virtual central processing unit (CPU) and a second virtual CPU, where at least one of the set of the first virtual CPU and the second virtual CPU spans across a first physical processing unit and a second physical processing unit. One or more resources from the first and second virtual CPUs are allocated to a first partition and a second partition. Whether one or more processes running on the first partition can utilize additional resources is determined. One or more resources from the first virtual CPU and resources from the second virtual CPU are reallocated to the first partition, where at least one of the resources was previously allocated to the second partition.

Abstract: An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.

Abstract: A method for providing a secure single sign-on to a computer system is disclosed. Pre-boot passwords are initially stored in a secure storage area of a smart card. The operating system password, which has been encrypted to a blob, is stored in a non-secure area of the smart card. After the smart card has been inserted in a computer system, a user is prompted for a Personal Identification Number (PIN) of the smart card. In response to a correct smart card PIN entry, the blob stored in the non-secure storage area of the smart card is decrypted to provide the operating system password, and the operating system password along with the pre-boot passwords stored in the secure storage area of the smart card are then utilized to log on to the computer system.

Abstract: A method and system for managing an intrusion on a computer by graphically representing an intrusion pattern of a known past intrusion, and then comparing the intrusion pattern of the known intrusion with a current intrusion. The intrusion pattern may either be based on intrusion events, which are the effects of the intrusion or activities that provide a signature of the type of intrusion, or the intrusion pattern may be based on hardware topology that is affected by the intrusion. The intrusion pattern is graphically displayed with scripted responses, which in a preferred embodiment are presented in pop-up windows associated with each node in the intrusion pattern. Alternatively, the response to the intrusion may be automatic, based on a pre-determined percentage of common features in the intrusion pattern of the known past intrusion and the current intrusion.

Abstract: A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory.

Abstract: A method, system and computer program product for automatically alerting one or more recipients of the arrival of an individual to a known destination via a global positioning system (GPS) navigation device. To issue an accurate alert of arrival time and or distance, the device enables: (1) pre-selection of two or more locations from a plurality of mapped locations; (2) pre-selection of one or more devices to which an alert is to be sent when the GPS device passes through the pre-selected locations; and (3) pre-selection of a time during which the alert should be triggered. The device automatically sends an alert to one or more devices when the GPS device passes through the pre-selected locations during the pre-selected time period, wherein the alert informs the user of the one or more recipient devices that the individual (corresponding to the GPS device) has commenced a journey to the destination.

Abstract: A boot block that contains a first public key is activated and a system Basic Input/Output System (BIOS) that contains a second public key and a first digital signature is verified, the verifying being performed by confirming that the first and second public keys match. In response to a determination that the first and second public keys match, the BIOS is activated and a system image is loaded to a real device. The system image is verified by confirming that the first digital signature that is stored in the system BIOS matches a second digital signature that is stored in a mass storage device. In response to the first and second digital signatures matching, a virtual mass storage device is created. Control of the virtual mass storage device is transferred to a boot strap code in an operating system image and the operating system image is booted from the virtual mass storage device.

Abstract: A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular type of instructions, determines when at least a threshold number of the particular-type instructions is scheduled to be executed. The logic then automatically changes an execution cycle frequency of the specific pipeline stages from a first cycle frequency to a second, pre-established higher cycle frequency, which enables more efficient execution and higher execution throughput of the particular-type instructions. The cycle frequency of only the one or more functional stages are switched to the higher cycle frequency independent of the cycle frequency of the other functional stages in the processor pipeline.

Abstract: A method for efficiently calculating signal thresholds for use in signal processing is described. The method computes and stores a cumulative histogram and a weighted cumulative histogram. The method then provides a first estimate for a threshold based on a single ratio. The method next performs an iterative computation to get to the ultimate threshold result. Method iterations only require multiplication and addition operations on the stored values making the method well suited for implementation in fixed-point digital signal processors.

Abstract: A data processing system has a processor, a memory, and an instruction set architecture (ISA) that includes: an asynchronous memory mover (AMM) store (ST) instruction that initiates an asynchronous memory move operation that moves data from a first memory location having a first real address to a second memory location having a second real address by: (a) first performing a move of the data in virtual address space utilizing a source effective address a destination effective address; and (b) when the move is completed, completing a physical move of the data to the second memory location, independent of the processor. The ISA further provides an AMM terminate ST instruction for stopping an ongoing AMM operation before completion of the AMM operation, and a LD CMP instruction for checking a status of an AMM operation.

Abstract: A system, method and computer-readable medium for adapting command line output message streams in a virtualized command line interface (CLI) environment. In accordance with the method of the present invention, a virtualized CLI command is entered and executed. The virtualized CLI command encapsulates a guest operating system command having an associated standard output message. In response to executing the virtualized CLI command, the standard output message is piped to an output message file. Within the standard output message file, a structured array is used to search the standard output message for matches between strings within the standard output message and one or more specified message strings identified in the structured array. In response to finding a match between the specified message strings and the strings within the standard output message, the specified message string within the standard output message is replaced with a replacement message string.

Abstract: A method of invoking power processor element (PPE) serviced C library functions on a synergistic processing element (SPE) running in isolated mode. When the SPE initiates a PPE-serviced function, an SPE stub routine allocates a parameter buffer in an open area of a local store (LS) memory within the SPE. The LS memory includes an open area accessible to the PPE, and an isolated area inaccessible to the PPE. The SPE stub routine copies function parameters corresponding to the PPE-serviced function to a buffer within the open area of the LS memory, and writes a message word, which contains an identification variable of the PPE-serviced function and a location variable of the function parameters, to the open area. When execution is temporarily suspended on the SPE, the PPE reads the message word from the open area of the LS memory and executes the PPE-serviced function.

Abstract: A portable electronic device having a display screen capable of changing display directions is disclosed. The portable electronic device, such as a tablet personal computer, includes a tiltmeter, a display direction determining circuit and a display direction changing circuit. The tiltmeter measures a first tilt angle of a first axis of a display screen of the portable electronic device with respect to a horizontal plane, and measures a second tilt angle of a second axis of the display screen of the portable electronic device with respect to the horizontal plane. The display direction determining circuit determines whether or not a display direction of the display screen is to be changed based on the changing conditions generated by the first tilt angle and the second tilt angle as measured by the tiltmeter.

Abstract: A method for performing a logical built-in self-test of an integrated circuit is disclosed. The method includes performing a flush and scan test to determine whether the scan chains function correctly. If one of the scan chains does not function correctly, the logical built-in self-test is terminated. If each of the scan chains functions correctly, a structural test of the design-for-test logic supporting LBIST is performed to determine whether the LBIST design-for-test logic functions correctly. If the LBIST design-for-test logic does not function correctly, the logical built-in self-test is terminated. If the LBIST design-for-test logic functions correctly, a level sensitive scan design test of the functional combinational logic is performed using the logic supporting LBIST design-for-test to determine if the integrated circuit functions correctly.

Abstract: A memory subsystem completes multiple read operations in parallel, utilizing the functionality of buffered memory modules in a daisy chain topology. A variable read latency is provided with each read command to enable memory modules to run independently in the memory subsystem. Busy periods of the memory device architecture are hidden by allowing data buses on multiple memory modules attached to the same data channel to run in parallel rather than in series and by issuing reads earlier than required to enable the memory devices to return from a busy state earlier. During scheduling of reads, the earliest received read whose target memory module is not busy is immediately issued at a next command cycle. The memory controller provides a delay parameter with each issued read. The number of cycles of delay is calculated to allow maximum utilization of the memory modules' data bus bandwidth without causing collisions on the memory channel.

Abstract: A optical disc drive is disclosed. The optical disc drive includes a housing and a tray configured to accommodate a disc therein. The optical disc drive also includes an automatic return-type eject switch, a drive controller, and an eject controller. Mounted in the housing, the automatic return-type eject switch is configured to generate an eject signal. In response to the eject signal, the drive controller ejects the tray. In response to the eject signal, the eject controller supplies an electric power to the optical disc drive, and transmits a pseudo eject signal to the drive controller to eject the tray by way of a line through which the eject signal has been transferred after a predetermined time period from the supply of the electric power has lapsed.