Patents Represented by Attorney Dolly Y. Wu
  • Patent number: 7400870
    Abstract: A hardware control loop (19) derives an AGC setting for a communication receiver based on signal strength information (16), without incurring program execution delay of a baseband processor.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: July 15, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Bernd Scheffler
  • Patent number: 7379374
    Abstract: A method of operating a memory circuit having a plurality of blocks of memory cells (400-404) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells (400) is selected in response to a first address signal (RAY0). A row of memory cells (430-436) in the first block of memory cells is selected in response to a second address signal (RAX0). A first voltage is applied to a first power supply terminal (412) of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal (412) of another block of memory cells (402) of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: May 27, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Hiep V. Tran
  • Patent number: 7372307
    Abstract: A current monitoring circuit for DC-DC switching converters includes a track and latch comparator circuit (30) having a preamplifier (32) that is controlled independently of a latch circuit (34). The comparator is small and operates very fast and with improved sensitivity. For example, the preamplifier circuit is disabled when the latch stage is making its decision to avoid noise and input disturbances from affecting the latch stage. This selective disabling feature speeds up the signal processing of the comparator and allows it to work in parallel with other circuits. The latch stage can make its decision later, regardless of any further activity at the inputs of the comparator.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: May 13, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Dolly Y. Wu
  • Patent number: 7336640
    Abstract: A CDMA receiver (500) minimizes the use of hardware by taking advantage of the fact that Walsh sequences of a predetermined length (e.g., 16) are comprised of inverted and non-inverted versions of smaller length (e.g., 4) sequences. The receiver (500) performs the necessary uncovering operations for example of a Walsh sequence of length 16 by performing uncovering operations using smaller length Walsh sequences such as of length 4 and then performing subsequent summing operations with inverted and non-inverted versions of the results of such uncovering operations.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: February 26, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: John G. McDonough, Jane Wang
  • Patent number: 7327185
    Abstract: An electronic system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply. The system further comprises a first circuit for providing a first value indicating a first potential capability of operational speed of at least one path in the plurality of circuit paths and a second circuit for providing a second value for indicating a second potential capability of operational speed of the at least one path in the plurality of circuit paths. The system further comprises circuitry for adjusting the system voltage, as provided by the voltage supply, in response to a relation between the first value and the second value.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: February 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Hugh Mair, Sumanth Gururajarao
  • Patent number: 7315601
    Abstract: A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: January 1, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Paul H. Fontaine, Abdellatif Bellaouar, Bertan Bakkaloglu
  • Patent number: 7301715
    Abstract: Managing temperature of a read/write head (120) in a disk drive system in which there is a power variance due to different operation modes. A circuit device (100) determines and delivers additional power needed for compensating for the temperature variance due to different operational power requirements. The power is delivered to a resistive heater (Rheat) associated with the head (120). The compensating power is based on the delivery voltage, delivery current, and resistance of the resistive heater (Rheat). The delivery current is varied to account for changes in the resistance of the resistive heater (Rheat) since it can vary with temperature. By sensing the current with a sensor (13), the resistance is determined via the sensed current and the delivery voltage. The current is adjusted for maintaining the compensating power.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: November 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Congzhong Huang, Bryan E. Bloodworth, Mike Sheperek
  • Patent number: 7301722
    Abstract: A disk drive actuator circuit adapted to retract a head assembly when a capacitor discharges energy to the voice coil. This voltage may be modulated to deliver peak torque to get the actuator over a ramp, yet also deliver a lower torque to suppress the initial head velocity when the actuator is over the disk.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: November 27, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Masaki Yamashita, Chisako Ota
  • Patent number: 7298777
    Abstract: This disclosure is generally directed to communication systems, devices used in communication systems and associated methods which may implement parallel hypothesis search techniques. The disclosed parallel hypothesis search techniques may permit a hypothesis to be dismissed early (i.e., before hypotheses in other searchers have completed their evaluation). Early hypothesis dismissal permits a new hypothesis to be loaded into the searcher while other searchers advantageously continue to evaluate their hypotheses.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: November 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: John G. McDonough, Gibong Jeong, Karim Abdulla, Rajiv R. Nambiar, William S. Clark, Jr.
  • Patent number: 7299358
    Abstract: A computing platform (10) protects system firmware (30) using a manufacturer certificate (36). The manufacturer certificate binds the system firmware (30) to the particular computing platform (10). The manufacturer certificate may also store configuration parameters and device identification numbers. A secure run-time platform data checker (200) and a secure run-time checker (202) check the system firmware during operation of the computing platform (10) to ensure that the system firmware (30) or information in the manufacturer certificate (36) has not been altered. Application software files (32) and data files (34) are bound to the particular computing device (10) by a platform certificate (38). A key generator may be used to generate a random key and an encrypted key may be generated by encrypting the random key using a secret identification number associated with the particular computing platform (10). Only the encrypted key is stored in the platform certificate (36).
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: November 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Alain Chateau, Jerome Azema, Constantin Haidamous
  • Patent number: 7295622
    Abstract: System and method for decoding received information using batched processing of independent parameters. A preferred embodiment comprises a decoder (for example, decoder 210) with a memory (for example, memory 215) that may be partitioned into a plurality of parts, one of which being a parameter partition (for example, parameter partition 217). A digital signal processor (for example, DSP 205) programs the decoder 210 with various ways that it wishes received data to be decoded and the decoder 210 can operate independent of the DSP 205, storing the results of each decoding operation in a specified location. At specified instances, the decoder 210 interrupts the DSP 205 to allow the DSP 205 to retrieve the decoding results.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: November 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: John G. McDonough, Glbong Jeong, Der-Chieh Koon
  • Patent number: 7295576
    Abstract: A transport packet parser (42) includes a transport packet header decoder (50) for identifying a packet identifier (PID) and continuity counter (CC) associated with a current packet. The PID along with an enable (En) bit is input to an PID associative memory (52) in search mode to identify an address associated with the PID. The address is used to access a CC associated with a previous packet for the same PID in a random access memory (62). The previous continuity counter is used along with other header information to determine whether the current packet satisfies predetermined criteria. If so, the packet is passed to a transport packet buffer for further processing.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: November 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Gerard Chauvel
  • Patent number: 7292652
    Abstract: System and method for detecting symbols wherein there may be a large frequency error. A preferred embodiment includes receiving an estimated frequency error, calculating a vector based on the estimated frequency error, buffering symbols from two symbol streams, rotating the symbols from the two symbol streams using the vector, estimating a channel gain for the symbols in the second symbol stream, and applying the channel gain to the rotated symbols from the second symbol stream.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: November 6, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Tao Luo, Young-Chai Ko, Gibong Jeong
  • Patent number: 7280330
    Abstract: An electrostatic discharge (ESD) device for protecting a power amplifier circuit is disclosed. The ESD device comprises a first ESD protection circuit coupled between a positive terminal of a supply voltage and a negative terminal of the supply voltage, and a second ESD protection circuit coupled between the negative terminal of the supply voltage and an output terminal of the power amplifier circuit, wherein a first current path is formed from the positive terminal to the output terminal through the first and second ESD protection circuits. A circuit device operative to increase impedance of a second current path from the positive terminal to the output terminal through the power amplifier circuit to divert current from the second current path to the first current path in the course of an ESD event.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: October 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Ismail H. Oguzman, Charvaka Duvvury, Chih-Ming Hung
  • Patent number: 7265926
    Abstract: A disk drive data storage system, comprising a magnetic disk a head for writing data to the disk, and circuitry for providing a first voltage (HWX) to a first node (N1) and a second voltage (HWY) to a second node (N2). The first and second voltage circuitry comprises a first transistor (421P2) of a first type and coupled to the first node, a first transistor (422N2) of a second type and coupled to the second node, a second transistor (441P2) of the first type and coupled to the second node, and a second transistor (442N2) of the second type and coupled to the node. The system also comprises circuitry for providing, during a first time period, a first biasing signal (VNDY) and a second biasing signal (VPDY) and circuitry for providing, during a second time period, a third biasing signal (VNDX) and a fourth biasing signal (VPDX).
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: September 4, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Reza Sharifi
  • Patent number: 7259609
    Abstract: A clamping circuit containing a transistor and a current amplifier. The transistor is designed to turn on when the voltage at a node exceeds (falls below) a specified upper (lower) level. The current amplifier is designed to draw substantial amount of current when the transistor is turned on to clamp the voltage at the node to the desired level.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: August 21, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Visvesvaraya A. Pentakota, Vineet Mishra, Shakti Shankar Rath, Gautam Salil Nandi
  • Patent number: 7230452
    Abstract: A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a third transistor. The second transistor is coupled to provide a control input to drive the first transistor to the conductive state thereof in response a first input signal provided at a control input of the second transistor. The third transistor is coupled to provide an output at the output node in response to a second input signal provided at a control input of the third transistor, the first and second input signals being out of phase with each other. Circuitry is coupled between the input supply node and the control input of the first transistor to provide reduced impedance at the control input of the first transistor according to operation of the second transistor.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: June 12, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Siew Kuok Hoon, Franco Maloberti, Jun Chen
  • Patent number: 7212139
    Abstract: A novel and useful method and apparatus for suppressing aliasing interferers in decimating and sub-sampling discrete time systems. The present invention is operative to reduce the requirements for or completely eliminate the need for the anti-aliasing filter by dynamically modifying the sub-sampling rate (or decimation ratio). Rather than maintain a constant sampling rate (or decimation ratio), the sampling rate (or decimation ratio) is randomized such that its average remains at the nominal value and the effective jitter is low enough for the low rate (or low decimation ratio) system to tolerate. This smears or spreads interfering signals across the spectrum resulting in a noise floor at a significantly reduced level much lower than that of the original interferer signal. The interfering signals are reduced to background noise wherein the level of the resulting noise floor is not nearly as strong as the original interfering signal.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: May 1, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Ran Katz
  • Patent number: 7205924
    Abstract: A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sudheer K. Vemulapalli, John Wallberg, Prasant K. Vallur, Robert B. Staszewski
  • Patent number: 7203797
    Abstract: A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: April 10, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gerard Chauvel, Maija Kuusela, Dominique D'Inverno