Abstract: An improved switched capacitor circuit configuration is disclosed which exhibits improved low voltage supply operation and improved charge injection cancellation performance. In the preferred embodiment of a switched capacitor integrator, the improvement is realized by the particular configuration of a switched tub switch on the input, single N-channel devices at the summing junction, skewing the analog ground V.sub.AG downward, and delaying the clock signals to turn off the switches at the summing junction before the charge injection of the switched tub switch is realized.

Abstract: A system for rapidly detecting power disturbances with ferroresonant transformers having a decay profile comprising the steps of rectifying a power signal; comparing the rectified signal against a reference signal; comparing the rectified signal against a dynamic reference signal; and generating a power-fail signal in response to either comparison falling below its respective reference.

Abstract: A CMOS data clock oscillator circuit is disclosed which provides a simple, inexpensive, high-specification oscillator with an accurate duty cycle. The data clock oscillator 100 includes an oscillator stage 121 providing an AC output signal having an average DC value determined by an applied bias voltage, a limiting stage 124 having MOSFETs 102 and 103 configured to form a back-to-back limiter network to limit the amplitude of the AC output signal, a CMOS biasing stage 122 including complementary MOSFETs 104 and 105 configured to form an active resistor voltage divider network providing the bias voltage for the oscillator stage, and a CMOS buffer stage 123 including complementary MOSFETs 106 and 107 configured to form an inverting amplifier network having a predefined input switching threshold. Buffer stage MOSFETs 106 and 107 have conduction types, geometries, and device parameters matched to those of bias stage MOSFETs 104 and 105, respectively.

Abstract: A differential input circuit for a switched capacitor CMOS voltage comparator is provided which minimizes offset voltages by configuring the load devices to utilize a single switched capacitor biasing network initialized from internally-generated bias voltages, while configuring the initialization switches for the differential input devices to also utilize internally-generated bias voltages such that the offset voltages are stored on the input capacitors. The power supply rejection performance of the voltage comparator is also optimized by connecting parallel load devices of opposite switching topology such that the same input impedance is seen at both load terminals.

Abstract: A system for assembling a hard crystal blank onto a base which includes connecting pins, using an apparatus providing self-locating and self-fixturing features, is described. The apparatus comprises a hard crystal blank supporting structure which provides vertical, horizontal and transverse locating features. The vertical, horizontal and transverse locating features are contiguous to the crystal supporting structure and locate the hard crystal blank to the crystal supporting structure. The hard crystal blank once located may be secured to the crystal supporting structure with a suitable adhesive. Connecting features for securing the crystal supporting structure to the base are provided. Once the crystal supporting structure has been secured to the base, the vertical, horizontal and transverse locating features are separated from the crystal supporting structure. The hard crystal blank and crystal supporting structure so assembled are precisely aligned to the base.

Abstract: A method and apparatus for determining which sector antenna of a sectorized cellular radiotelephone system is receiving the strongest radio signal is disclosed. The signal strength of sector antennas is sequentially sampled, converted to digital representations, and stored according to which antenna received the signal. The digital representations are recalled from storage and the strongest signal along with an identification of the receiving antenna are determined. This determination may be used in the handoff process or in detecting when a remote unit requires a handoff.

Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.

Abstract: A paging system providing an LPC encoded speech output having an adaptive bit rate. The LPC bit rate is adaptively modified based on paging system airtime loading. Synthesizer circuitry in the paging receivers, together with a system signalling scheme is used to update the paging receivers as to the LPC bit rate, allows the paging receiver to decode the adaptive bit rate signal.

Abstract: Disclosed is a signalling system wherein a private call initiating trunked subscriber enters a private ID number on an entry means. The trunked subscriber unit decodes the entered number and forms the ID code required to request a channel. The central controller receives the request and encodes an appropriate channel grant for a trunked private call. In another aspect of the present invention, the called subscriber unit may decode and display the ID of the calling subscriber.

Abstract: An ultra high density pad array chip carrier is disclosed which includes a ceramic substrate having a plurality of electrical conductors each of which connect to a respective through-hole plugged with solder on its bottom surface. These solder plugs form a pad array for the chip carrier as well as provide a hermetic seal for the ceramic substrate. A polymer dielectric layer is affixed to the top surface of the ceramic substrate which provides an insulated metal die mount pad thereon. The electrical conductors on the ceramic substrate are formed using well-known vacuum metallization techniques to achieve much narrower widths. Approximately a 40 percent reduction in overall size and cost is achieved utilizing this improved arrangement, which improves reliability and facilitates post-assembly cleaning of the chip carrier when mounted to its final board.

Abstract: A console interface for a trunked communication system is disclosed wherein unique interface modules are coupled to the central controller and console network to establish communication therebetween. A console interface constructed and arranged to transceive trunking channel call information couples the dispatcher console to the console network thereby allowing the dispatcher to interact with the trunked system.

Abstract: An improved simulcast transmission system having automatic synchronization is disclosed which utilizes a signal from any one of a number of readily available master timing sources to maintain a constant, uniform time delay to a multiplicity of transmitters even though the time delay corresponding to an included individual interconnect link is susceptible to variation. This simulcast system includes a central controller for controlling, via an interconnect link, the operation of each transmitter located at a plurality of base station sites. This central controller includes a master timing signal receiver and periodically outputs a resynchronization command via the interconnect link to the base stations. Each interconnect link may consist of a phone line or other radio link which exhibits a relatively fixed, but unstable, delay.

Abstract: A simulcast transmitter apparatus having automatic synchronization capability is disclosed which utilizes a signal readily available from any one of a number of available master timing sources to maintain a constant, uniform time delay to the transmitter via its interconnect link, even though the time delay corresponding to this interconnect link is susceptible to variation. Each interconnect link may consist of a phone line or other radio link which exhibits a relatively fixed, but unstable, delay. Each base station includes at least a transmitter and an adaptive-delay device which operates as a remotely-adjustable delay network upon receipt of a resync signal from a central controller to readjust and automatically maintain a uniform amount of time delay to each transmitter in the base stations.

Abstract: A solder paste dispensing assembly provides for the controlled application of a predetermined solder paste pattern to a surface. The surface can be on a printed circuit board, prior to or after the board is mounted onto an assembled product or it can be a portion of the product itself. The surface can be a planar or non-planar surface.

Abstract: A multiresonator dielectric block filter is disclosed in which capacitive coupling between foreshortened resonators disposed in the dielectric block is controlled by an electrode strip coupled to the conductive material covering the majority of the dielectric block surface. The electrode strip extends at least partially between two adjacent resonators to control the capacitive coupling between the resonators.

Abstract: A control or front panel assembly which is suitable for inclusion in associated apparatus. The panel assembly includes a switching arrangement with individual switch actuators easily detachable and removable during final assembly prior to mounting an escutcheon plate to the front panel face. In this manner, a single piece part need only be inventoried, modifiable during final assembly, to effect the desired model variations for the associated apparatus.

Abstract: An adaptive phase locked loop being particularly useful with low frequency input signals, the adaptive phase locked loop including a phase comparison unit (12) for comparing a component of the input signal with the reference signal having an average phase, a polarity detection unit (14) for providing a polarity indication signal dependent upon the polarity of the output signal, and a reference signal unit (13) for providing a reference signal having an average phase to the phase comparison unit (12). In response to the polarity indication signal, the reference signal unit (13) can vary the rate at which the average phase of the reference signal can be changed at either of two rates, with the first rate representing a relatively slow rate and the second rate representing a relatively fast rate.

Abstract: An improved synchronization method and apparatus is disclosed which derives a common reference signal from a pilot frequency which is embedded among other signal information and which may be preselected from among a group of possible pilot frequencies utilized in multiplexing and demultiplexing groups of information signals on a RF communication system. One such arrangement as disclosed provides for rapid phase-lock acquisition with very few functional blocks by utilizing a linear multiplier as a phase detector at the generally higher pilot frequency rather than the much lower reference frequency. Another embodiment discloses a method and arrangement for providing automatic leveling of the pilot frequency input signal using a second linear multiplier as an amplitude detector.