Abstract: A spinal disk implant comprises a solid body having four faces arranged to define a right-rectangular solid body and two faces that define the ends of the solid body. The faces that define the right-rectangular body include two opposed side faces and two opposed transverse faces. The transverse faces have a central region with three-dimensional features thereon and an anterior platform region lying along an anterior margin of the transverse faces. The faces defining the ends of the solid body include a convexly curved anterior face and a posterior face. The solid body is made of a biocompatible synthetic material. A kit that may be used by a surgeon includes an implant and an implant delivery tool dimensioned to releasably hold the implant.

Abstract: A spinal disk implant is implanted between vertebrae of the human spine following discectomy. The implant comprises a solid body having four sides and a pair of spaced-apart, opposed bases. The four sides include spaced-apart, opposed anterior and posterior faces, and a pair of spaced-apart, opposed transverse faces. Each transverse face has an anterior platform adjacent to the anterior face. The anterior platform is spaced apart from the opposed anterior platform by a maximum anterior platform spacing. A posterior ledge is oriented at an insertion angle relative to an opposed posterior ledge of the opposed transverse face. At least one of the posterior ledges has a pattern of serrations. There is a ridge on at least one of the transverse faces, positioned between the anterior platform and the posterior ledge and extending in the direction perpendicular to the bases. The top of the ridge is spaced apart from the opposed transverse face by an amount greater than the anterior platform spacing.

Abstract: A system for backing up volatile memory such as DRAM with non-volatile memory such as EEPROM includes a volatile memory having refresh logic for cycling through the volatile memory address locations and refreshing the contents thereof, and a non-volatile memory having write logic for writing data into an address location of the non-volatile memory over a write cycle. Each of the volatile and non-volatile memories has its own address bus, and the address buses are connected together for reading out the contents of corresponding address locations of the two memories in the same sequence according to the cycle dictated by the volatile memory refresh logic.

Abstract: A semiconductor integrated circuit device has an on-chip processor and at least one on-chip digital register for storing plural bits therein. The bit contents of the register are written, selectively transformed, and read out of the register during processing of data by the processor and related circuitry. Peripheral instructions such as those from an interrupt source may contend with instructions from the processor for setting and clearing one or more bits in the register. To permit setting and clearing a unique bit in the register without affecting other bits in the register or the capability of the contending source to perform its instructions on one or more of these other bits, three separate addresses are provided for bit set, bit clear, and direct write of the register.

Abstract: A silicon substrate with a drain area formed therein is used for the base of the device. A first polysilicon gate is disposed above the substrate with a layer of gate oxide therebetween. Adjacent to the first gate and contiguous to the same plane is a second polysilicon gate. The second gate and the substrate are separated by a layer of tunnel oxide and silicon nitride. The silicon nitride being used to store a charge. The state of the device is determined by the presence of a capacitance in the substrate generated by the charge on the silicon nitride. This device may function as a nonvolatile memory or a dynamic random access memory with the capability of capturing its DRAM state.

Abstract: The processor executes programs from an internal EEPROM or from an external source. The EEPROM can be read either by a special operating (test) mode of the processor or by an instruction executing under normal operating mode from the EEPROM or from an external source. Similarly, the EEPROM can be programmed (written) either by a special operating mode or by under a normal operating mode instruction. The read and write circuits for the EEPROM are controlled to provide two levels of security against piracy of programmed information. In the first level, access is prevented for the read and write test modes and also for the read and write normal operating instructions if the instructions originate from an external source. In the second level, program execution from external source is also disabled.

Abstract: An implantable cardiac stimulator integrates the functions of bradycardia and anti-tachycardia pacing-type therapies, and cardioversion and defibrillation shock-type therapies. The stimulator is programmable to provide a multiplicity of hierarchical detection algorithms and therapeutic modalities to detect and treat classes of ventricular tachycardia according to position within rate range classes into which the heart rate continuum is partitioned, and thus according to hemodynamic tolerance, with backup capabilities of defibrillation and bradycardia pacing at the higher and lower regions of the rate continuum outside the range of the ventricular tachycardia classes. Aggressiveness of the therapy is increased with elapsed time and increasing heart rate, and detection criteria are relaxed with increasing heart rate and thus with increasing hemodynamic intolerance of the tachycardia.

Abstract: A pair of defibrillation patch electrodes is adapted for close fitting placement over the ventricles of the heart, either epicardially or pericardially. One of the patches is contoured to fit over the right ventricle, and the other is contoured to fit over the left ventricle in spaced relationship to the first patch to form a substantially uniform gap between confronting borders of the two. The gap is sufficiently wide to avoid the shunting of current between edges of the patches upon delivery of defibrillation shocks, as well as to accommodate the ventricular septum and the major coronary arteries therein. The size and shape of the patches is such that they encompass most of the ventricular myocardium within and between their borders, to establish a nearly uniform potential gradient field throughout the entire ventricular mass when a defibrillation shock is delivered to the electrodes. Flat versions of the two electrodes provide ease of manufacture.

Abstract: In a method and apparatus for defibrillating a heart in fibrillation, the onset of fibrillation of the heart is detected, and a biphasic waveform having only a first phase and a second phase is applied to the fibrillating heart. Each phase of the waveform is characterized by a predetermined time duration and by a predetermined polarity and magnitude of voltage, the duration of the first phase being greater than the duration of the second phase, and the initial voltage magnitude of the first phase being greater than that of the second phase. The biphasic waveform is applied by delivering it to a pair of patch electrodes affixed over and contoured to conform substantially to the surface of the right and left ventricles, respectively. The patch electrodes are affixed to either the epicardium or the pericardium. The left ventricular patch electrode is used as the cathode for the first phase of the applied biphasic waveform, and as the anode for the second phase.