Patents Represented by Attorney, Agent or Law Firm Donna L. Angotti
-
Patent number: 7090432Abstract: A spill containment and remediation system. A reel for a boom is mounted in the upper part of a weatherproof housing. The lower region of the housing is leakproof and can store recovered liquid spill. A boom or dike is mounted on the reel. The housing has an opening which is normally sealed shut by a door. The housing is configured to be mounted on the exterior of a tanker delivery truck. When a spill occurs the door is opened and the boom readily deployed through the opening. After use, the containment boom can be reeled-in and stored over the lower region of the housing.Type: GrantFiled: September 17, 2002Date of Patent: August 15, 2006Inventor: Edwin Christopher Jackson
-
Patent number: 6626723Abstract: The difference of luminance between a front surface side and a rear surface side as viewed from the front surface side is reduced in a multi-layered EL lamp. An EL lamp includes a first laminate formed by serially laminating a first transparent electrode, a first luminescent layer and a first insulating layer, a second laminate formed by serially laminating a second transparent electrode, a second luminescent layer and a second insulating layer on the first laminate, and a rear electrode formed on the second laminate, wherein a dielectric constant between the first and second transparent electrodes is set to a value smaller than a dielectric constant between the second transparent electrode and the rear electrode.Type: GrantFiled: August 9, 2002Date of Patent: September 30, 2003Assignee: Seiko Precision, Inc.Inventor: Koji Yoneda
-
Patent number: 6601513Abstract: A motor control method and apparatus for stopping an object moved by a motor accurately at a predefined target position, shortening the time period required in stop control, in which the motor is driven at a first (high) speed up to a distance from the target position adequate for stop control and then is sequentially braked to a predetermined speed lower than the first speed, driven at a second (low) speed up to a distance from the target position equal to the stopping distance, and braked to a stop. The method and apparatus are used in a time recorder. An impact printing apparatus is also disclosed with printing pin actuation timing correction dependent upon scanning speed or platen shape, striking duration timing dependent upon scanning rate, or printing pin actuation timing dependent upon stored shift amounts.Type: GrantFiled: May 24, 2000Date of Patent: August 5, 2003Assignee: Seiko Precision, Inc.Inventor: Kenji Ozawa
-
Patent number: 6595653Abstract: A light illuminating type switch with a good click rate and having a desired click characteristic near to that of a single member of a metal dome. Fixed contacts 7a are provided on a base sheet 7. On an upper side of the base sheet 7, a dome shaped movable contact 8 capable of electrically connecting the fixed contacts 7a on the base sheet by being elastically deformed is arranged. The surface of the dome shaped movable contact 8 is attached with a flexible EL sheet E by using adhering agents 9a and 9b via an insulating member 6 over a peripheral portion of the dome shaped movable contact 8. The EL sheet E is formed with cut portions 10 partially at positions along an outer peripheral edge of the dome shaped movable contact 8. At least a pair of the cut portions 10 are formed at symmetrical positions centering on the movable contact 8.Type: GrantFiled: August 6, 2001Date of Patent: July 22, 2003Assignee: Seiko Precision Inc.Inventors: Atsushi Saito, Yasufumi Naoi
-
Patent number: 6565334Abstract: A counter-rotating axial flow fan for cooling electronic components comprising two or more impellers with narrow chord blades. At least one impeller rotates in a first direction and at least one impeller rotates in a second direction opposite to the first direction. The blades of the impellers are configured so as to cause air to flow in the same axial direction. The air flow generated by this counter-rotating fan is substantially greater than the air flow of an otherwise identical co-rotating fan.Type: GrantFiled: July 23, 2001Date of Patent: May 20, 2003Inventors: Phillip James Bradbury, Phep Xuan Nguyen, Chalmers R. Jenkins, Scott H. Frankel
-
Patent number: 6559698Abstract: To restrain cycle-to-cycle jitter in a clock generator subjected to EMI a 2nd order PLL having a loop filter including a first capacitor and a first resistor, is provided where a reduction in a comparison frequency is avoided by using a clock modulating circuit. The clock modulation circuit is controlled by an intermediary signal provided by dividing an oscillation signal of a voltage controlled oscillator. The output of the clock modulation circuit is used to recurrently control a divider for dividing the output of the voltage controlled oscillator. Generation of high frequency noise is minimized by using a 1st order &Dgr;&Sgr; modulator(21) in the clock modulation circuit. The system behaves like a 3rd order PLL due to the presence of a second capacitor having a capacitance value of about {fraction (1/10)} or more than that of the first capacitor. The second capacitor is placed in parallel with the loop filter to restrain the cycle-to-cycle jitter by effectively removing the high frequency noise.Type: GrantFiled: October 17, 2000Date of Patent: May 6, 2003Assignee: Nippon Precision Circuits, Inc.Inventor: Satoru Miyabe
-
Patent number: 6515522Abstract: A drive circuit capable of adjusting a capacitive load operation, for example, respective brightness of an electroluminescence (EL) element. The drive circuit is a constant current drive system and causes a plurality of capacitive loads, for example, EL elements, to emit light. This is done by setting a coil drive signal applied to the gate of a transistor Tr1. The transistor generates a surge pulse by intermittently connecting a direct current power source to a coil L1 of a step-up circuit 1. The coil drive signal is set to a frequency in accordance with an EL element as a capacitive load driven alone or a combination of EL elements simultaneously driven. Power generated by the step-up circuit 1 can be selected, brightness of a driven EL element E1 or E2 can individually be set or brightness of the EL elements E1 and E2 simultaneously driven can be set.Type: GrantFiled: May 25, 2001Date of Patent: February 4, 2003Assignee: Nippon Precision Circuits, Inc.Inventors: Yoshiaki Inada, Masaaki Shibasaki
-
Patent number: 6476552Abstract: The difference of luminance between a front surface side and a rear surface side as viewed from the front surface side is reduced in a multi-layered EL lamp. An EL lamp includes a first laminate formed by serially laminating a first transparent electrode, a first luminescent layer and a first insulating layer, a second laminate formed by serially laminating a second transparent electrode, a second luminescent layer and a second insulating layer on the first laminate, and a rear electrode formed on the second laminate, wherein a dielectric constant between the first and second transparent electrodes is set to a value smaller than a dielectric constant between the second transparent electrode and the rear electrode.Type: GrantFiled: April 13, 2000Date of Patent: November 5, 2002Assignee: Seiko Precision, IncInventor: Koji Yoneda
-
Patent number: 6469564Abstract: A circuit simulating the function of a diode in the sense that it conducts current in one direction and blocks current in the opposite direction, but which has a low forward voltage drop. A voltage comparator and a three terminal switch are connected so that the intrinsic reverse diode associated with the switch is harnessed to conduct current in the direction in which it is desired to conduct current and to block current in the direction in which it is desired to block current. A voltage comparator controls the control terminal of the three terminal switch to turn on the switch to conduct current and to interrupt current. Alternate embodiments of voltage comparators are disclosed. The voltage comparator may include charging and discharging transistors so that the switch turns on and off at a high speed. The invention further includes a method of conducting current in one direction and blocking current in a second direction which reduces power losses.Type: GrantFiled: May 9, 2000Date of Patent: October 22, 2002Assignee: Minebea Co., Ltd.Inventor: Arian M. Jansen
-
Patent number: 6453150Abstract: Antenna elements 20 are arranged at intervals “d” greater than &lgr;/2, e.g., 5&lgr;. A signal received by an antenna element 20 is sent by way of an antenna multiplexer 21 to a receiver 23, where the signal is demodulated. The thus-demodulated signal is sent to a phase-and-power detection section 25, where a phase and power of the signal are detected. On the basis of the result of such detection, a control section 26 calculates the phase and power of a transmission signal. On the basis of the result of the calculation, a transmission signal generation circuit 27 transmits a transmission signal to each of the antenna elements 20 by way of the antenna multiplexer 21.Type: GrantFiled: May 27, 1998Date of Patent: September 17, 2002Assignee: Kyocera CorporationInventors: Kazuhiro Yamamoto, Muneo Iida
-
Patent number: 6411172Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations, an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with.Type: GrantFiled: January 3, 2001Date of Patent: June 25, 2002Assignee: Nippon Precision Circuits, Inc.Inventors: Kunihiko Tsukagoshi, Satoru Miyabe, Kazuhisa Oyama
-
Patent number: 6397057Abstract: A information fulfillment system and method for providing information to a caller having a wireless communication device. Upon receipt of sensory prompting and manual or automatic input of access codes to the wireless communication device, the caller's identity and the input access code are verified. Thereafter, the call is connected through the PWN and along the PSTN to the system messaging or fulfillment center for automatic or live-operator delivery of the requested information. Automatic verification, connection, and billing modification processes are provided for implementation of the system and method.Type: GrantFiled: December 24, 1997Date of Patent: May 28, 2002Assignee: Ewireless, Inc.Inventors: James E. Malackowski, Kristi L. Stathis
-
Patent number: 6373008Abstract: A unitized light illuminating type switch in a thinned type and having enhanced click feeling. A movable contact and an electroluminescent sheet are formed in an integrated structure by attachedly pasting together the movable contact and the electroluminescent sheet. Fixed contacts are provided on a switch sheet. A movable contact capable of electrically connecting to the switch sheet by being elastically deformed is arranged above the switch sheet. A flexible electroluminescent sheet A is attachedly pasted to a surface of the movable contact by interposing an insulating member as far as a peripheral portion of the movable contact other than the movable contact.Type: GrantFiled: March 10, 2000Date of Patent: April 16, 2002Assignee: Seiko Precision, Inc.Inventors: Atsushi Saito, Yasufumi Naoi, Koji Yoneda, Kaori Aoki
-
Patent number: 6360657Abstract: A printer is capable of stably feeding even a thin recording medium to a printing section and obtaining good print quality similar to that obtainable in the case of a thick recording medium. The printer comprises a first supply path for supplying a first recording medium, a second supply path for supplying a second recording medium thicker than the first recording medium, a printing section for printing on a recording medium supplied from the first supply path or the second supply path, and a delivery section for delivering the recording medium printed in the printing section. A guide spring member which is movable up and down is projected upstream of the printing section and in a meeting portion of the first supply path and the second supply path. This guide spring member serves to support a top surface of the first recording medium at a predetermined height.Type: GrantFiled: August 31, 1999Date of Patent: March 26, 2002Assignee: Seiko Precision, Inc.Inventors: Naoki Tanabe, Satoru Tada
-
Patent number: 6360349Abstract: A syndrome computing apparatus includes first syndrome computing circuit 2, 4 for receiving a predetermined number of bits of data (codewords) encoded based on a predetermined generator polynomial and performing a syndrome computation on the data inputted based on the generator polynomial. Shift register 1 delays the data by the predetermined number of bits. Second syndrome computing circuit 3, 5 receives the data delayed by the predetermined number of bits, and performs a syndrome computation on the data inputted based on the generator polynomial. Operating circuit 7, 8 vector-adds modulo 2 a first syndrome outputted by said first syndrome computing means to a second syndrome outputted by said second syndrome computing means. Outputs of said operating means 6, 7 are offered as a syndrome based on the generator polynomial.Type: GrantFiled: May 22, 1998Date of Patent: March 19, 2002Assignee: Nippon Precision Circuits, Inc.Inventor: Hiroyuki Kawanishi
-
Patent number: 6351149Abstract: There is disclosed a MOS transistor output circuit capable of suppressing ringing and other noises and of operating at high speed under low power supply voltages. A signal corresponding to an input signal is applied to the gates of a first p-channel MOS transistor and a first n-channel MOS transistor. A control circuit detects the falling edge of the input signal to create a first signal. A second p-channel MOS transistor is held in conduction by the first signal during a period beginning with the rising edge of the output signal and ending with the instant at which the output signal can be regarded as having logic high (H) level. The rising edge of the input signal is detected to create a second signal. A second n-channel MOS transistor is held in conduction by the second signal during a period beginning with the falling edge of the output signal and ending with the instant at which the output signal can be regarded as having logic low (L) level.Type: GrantFiled: December 3, 1999Date of Patent: February 26, 2002Assignee: Nippon Precision Circuits, Inc.Inventor: Satoru Miyabe
-
Patent number: 6331724Abstract: A semiconductor memory cell device exhibiting superior cell reliability comprising a dual layer floating gate wherein the thin upper layer of the floating gate overlaps the edges of surrounding field insulating regions and has rounded edges to minimize leakage concerns. The tunnel dielectric separating the dual layer floating gate from the substrate comprises a layer of uniform thickness which is grown prior to the formation of the field insulating regions. The Fowler-Nordheim tunneling mechanism is used for programming and erasing the inventive cells in a programming process flow which comprises flash programming all cells on a word line, sensing current on a selected cell, and selectively erasing the charge on the cell by applying a higher voltage on the intersecting bit line than is applied to the word line, until the sensed current is as desired.Type: GrantFiled: December 23, 1997Date of Patent: December 18, 2001Assignee: Nippon Precision Circuits, Inc.Inventors: James T. Chen, Atsuo Yagi
-
Patent number: 6242980Abstract: The first amplifier circuit D1 is formed by connecting drains of a pair of N-channel MOS transistors forming the first current mirror circuit CM1 respectively to the drains of P-channel MOS transistors 1 and 2 as a differential input portion, and the second amplifier circuit D2 is formed by connecting drains of a pair of P-channel MOS transistors forming the second current mirror circuit CM2 respectively to the drains of N-channel MOS transistors 5 and 6 as a differential amplifier circuit. The first and second differential amplifier circuits D1 and D2 can amplify the first and second signals having cycles corresponding with each other with their duty ratios kept unchanged regardless of their operating point potentials. Further, the two outputs are combined into one output to suppress variation of the operating point potential of the output attributable to process-related factors, fluctuation of the power supply potential due to the oscillating operation and the like.Type: GrantFiled: November 18, 1998Date of Patent: June 5, 2001Assignee: Nippon Precision CircuitsInventors: Kunihiko Tsukagoshi, Satoru Miyabe, Kazuhisa Oyama
-
Patent number: 6191661Abstract: There is disclosed an oscillator circuit in which the first capacitor is connected between the input side of a CMOS inverter in a quartz oscillator circuit and a higher potential side, the second load capacitor is connected between the input side of the inverter and a lower potential side, the third load capacitor is connected between the output side of the inverter and the higher potential side, and the fourth load capacitor is connected between the output side of the inverter and the lower potential side, so that variation in amplitudes of the voltage sources synchronized with the oscillation can be reduced with the realization of lower current consumption. There is also disclosed an oscillator circuit of reduced circuit scale. A CMOS inverter for producing oscillations an AC coupling capacitor, and a buffer circuit are formed on one chip. A protective circuit that has been heretofore required at the input terminal portion of the buffer circuit can be dispensed with.Type: GrantFiled: December 21, 1998Date of Patent: February 20, 2001Assignee: Nippon Precision Circuits, Inc.Inventors: Kunihiko Tsukagoshi, Satoru Miyabe, Kazuhisa Oyama