Abstract: A FET package including one or more FETs includes an arrangement of three metallization layers for the gate, drain, and source terminals thereof. The layers include a gate runner metallizaton layer that allows the FETs to be arranged in a parallel manner so as to reduce the overall total on-state resistance to an optimum value, while allowing the gate switching capacitance to be increased to an optimized value. The gate runner metallization layer is arranged to minimize the overlapping capacitance between the gate and source terminals and between the gate and drain terminals. Additional semiconductor devices may be incorporated into the FET package using additional terminals interconnected through the metallization layers, thus providing additional functions.