Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A reluctance sensor produces reluctance signals in response to passing slots in a rotating wheel. When a given signal exceeds a threshold, a DIG.sub.-- OUT signal is produced. When the signal falls to zero, the DIG.sub.-- OUT signal is terminated. The invention adjusts the threshold, based on the magnitude of the reluctance signals. Since the magnitude of the reluctance signals depends on wheel speed, the invention, in effect, adjusts the threshold based on wheel speed, yet without independently measuring wheel speed.

Abstract: The invention concerns utilization of a single pin on an integrated circuit for a dual purpose. First, the pin carries data in a normal manner. Second, the pin carries a test signal, which is used, for example, to trigger a testing circuit into action. The invention receives both the data signals and the test signal. The invention ignores the data signals, and responds only to the test signals.

Abstract: A method for reducing the apparent response time for write I/O operations initiated by a host system to a RAID level 3, 4 or 5 disk array including a spare disk drive. The disclosed method comprises the steps of (1) saving write data received by the disk array from the host system directly to the spare drive, (2) issuing a write complete status signal to the host system indicating completion of the host write I/O operation, thus freeing the host processor to perform other functions, and (3) transferring the data saved to the spare drive to the active drives within the array. This third step may be executed at any convenient time following the second step. For example, in systems where a host processor functions as the array controller, this third step may be delayed while higher priority tasks are executed. In systems where the disk array includes an array controller, the array controller coordinates the execution of this third step with other controller or array operations to optimize array operation.