Abstract: A logic clock signal generator implemented with delay lines having a plurality of taps, wherein the taps are selectively feedback coupled to the input to produce a clock signal having a plurality of selectively variable time periods.

Abstract: A rework layer for a multi-layer printed circuit board comprised of a reference layer and a wire network containing a plurality of conductors tailored to match the impedance characteristics existing between the internal layers of the printed circuit board, wherein the conductors can be selectively terminated after fabrication of the printed circuit board.

Abstract: An AC to DC power supply having a multi-channel, flyback inverter output section regulated via a fixed frequency, pulse width modulation controller. The controller indirectly regulates each channel by regulating an auxiliary channel, whereby the duty cycle of a switching transistor in the flyback inverter section is varied to maintain a constant DC voltage on the auxiliary channel and correspondingly on each output channel.

Abstract: A mixtureand method are disclosed for growing bismuth lutetium iron garnet crystals via liquid phase epitaxy on a gadolinium gallium garnet (GGG) substrate wherein the crystals exhibit a relatively high Faraday rotation and an improved optical absorption.

Abstract: A rinse process for solvating adhered primary melt residue from magnetic garnet crystals grown via liquid phase epitaxial (LPE) techniques. The rinse melt consists of a mixture having a saturation to nucleation temperature range that encompasses the primary melt's growth temperature and a solvent compound different from that used in the primary melt, which will solvate the solvent used in the primary melt and will not produce undesirable rinse melt adhesion.

Abstract: A real time digital graphics display system is disclosed for generating circles, arcs and vectors. The system utilizes Taylor's formula to determine the successive coordinates of the points along the image of the character displayed. The system is able to display a given graphical character once given the coordinates of a start point, an end point and the number of increments to be displayed if an arc is to be displayed.

Abstract: An electrically and mechanically modular design of a high impedance, passive tap is disclosed for use in distributed, serial transmission systems to provide a tap connection to the primary transmission line with minimum loading and reflection. The tap is comprised of the cable connectors and a microstrip circuit compatible with an associated transceiver.

Abstract: A full wave (RMS) bridge circuit is disclosed for regulating a nominal 200 to 240 V AC bulk voltage to a nominal 300 V full wave rectified DC bulk voltage for all line and load conditions. The circuit automatically adjusts to varying line voltages and operates in any one of four modes: (i) full wave bridge, (ii) phase controlled bridge-doubler, (iii) phase controlled doubler, or (iv) non-controlled doubler to maintain the nominal DC output voltage.

Abstract: A common-emitter amplifier having its dynamic voltage gain controlled by using a controlled emitter-follower to shunt the emitter impedance of the common emitter amplifier.

Abstract: The disclosure teaches an improved connector containing a fold bushing for connecting an inner braid of a transmission line to its associated shield conductor within the connector and for minimizing the reflection signal induced by each connector affixed to the transmission line.

Abstract: An electrically and mechanically modular design of a high impedance, passive transceiver is disclosed for use in distributed, serial transmission systems to provide half uplex interfacing to multiple users with minimum loading and reflection. The transceiver is selectively operable in either of two modes: a receive mode for receiving low-level serial, bi-phase (3 state) Manchester coded signals and transmitting (2 wire, 2 state) signals at transistor-transistor logic (TTL) levels; and a transmit mode for receiving (2 wire, 2 state) signals at TTL levels and transmitting the low-level, serial bi-phase, (3 state) signals on the bus.

Abstract: A printed circuit board package for high density packaging of electronic circuit components is disclosed. The circuit components are cooled by a liquid cooled, cold plate with a compliant mat interface. The interface is made of a heat conductive, electrically insulative compliant structure, such that uniform contact can be made with the circuit components, even if there are differences in the relative heights and shapes of the components.

Abstract: An improved method is disclosed for etching the thick field insulator films of silicon-oxy-nitride, during the fabrication process of metal oxide semiconductor (MOS) devices, wherein a polycrystalline silicon etch mask is used in conjunction with an acid etchant to etch the gate and interconnect openings through the thick field insulator to the source, gate and chain regions of the MOS devices for a memory array.

Abstract: An improved sense latch circuit for differentially sensing an MNOS memory FET's voltage thresholds, selectively operable in either a memory retention or read interrogation mode with enhanced sensitivity and improved power conservation. The improvement consisting of the additional cross coupling of each of the latch outputs to a respective plurality of MOS FETs coupled in series with each of the MNOS FET inputs, which cross coupling reduces extraneous current paths and increases the switching sensitivity of the sense latch circuit.

Abstract: A convergence correction system is disclosed for digitally controlling the convergence correction signals applied to the convergence correction coils of a color CRT. The convergence correction signals correspond to a plurality of segments defined for the phosphor face of the CRT, so as to produce the convergence of the associated electron beams at the phosphor triads within the individual segments. The system provides for the independent adjustment of the convergence of each electron beam within each of the four quadrants of the phosphor face, independent of the adjustments for the convergence of the other electron beams. The system further provides for the use of only one convergence correction coil for each associated electron beam.